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[ak 4601 ] 016000391 - e - 0 1 - 1 - 201 6 / 12 1. general description the AK4601 is a n audio hub codec including 5ch adc, 6ch dac and digital mixers. the analog input block consists of a 24 - bit stereo adc, a 24 - bit stereo adc with input selector and a monaural adc, and the analog output block consists of 32 - bit 6ch dac. the t ransfer block for digital signals integrates a serial interface that supports d ata bus and tdm format, realizing an audio hub function. it gives scalability to the device for both analog and digital signals. a car audio system that is capable of processing both sound and voice such as for hands - free function simultaneously can be re alized by using the AK4601 with akm s multi - core dsp, the ak7707. the AK4601 is available in a space saving 48 - pin lqfp package. 2. features adc1: 24 - bit stereo adc with mic gain amplifiers - sampling frequency: fs=8khz to 192khz - channel independent analog gain amplifiers (0 to 18db(2db step), 18 to 36db(3db step)) - differential input or sin gle - ended input - adc characteristics s/n: 10 6 db (fs=48khz, differential input, mic gain=0db,) - channel independent digital volume control (+24 to - 103db, 0.5db step, mute) - digital hpf for dc offset cancelling - low noise mic power output: 2ch - 4 types of digital filter for sound color selection adc2: 24 - bit stereo adc with input selector - sampling frequency: fs=8khz to 192khz - analog input selector: differential input x1 or single - ended input x2, semi - differential input x1 - adc characteristics s/n: 10 6 db (fs=48khz, differential input) - channel independent digital volume (+24 to - 103db, 0.5db step, mute) - digital hpf for dc offset cancelling - 4 types of digital filter for sound color selection adcm: 24 - bit monaural adc - sampling frequency: fs=8khz to 192khz - differential input or single - ended input - adc characteristics s/n: 10 6 db (fs=48khz, differential input) - channel independent digital volume (+24 to - 103db, 0.5db step, mute) - digital hpf for dc offset cancelling - 4 types of digital filter for sound color selection dac: advanced 32 - bit dac - 2ch x 3 - sampling frequency: fs=8khz to 192khz - single - end ed output - dac characteristics s /n: 108db (fs=48khz) - channel independent digital volume control (+12 to - 115db, 0.5db step, mute) - 4 types of digital filter for sound color selection audio hub codec with digital mixer ak 4601
[ak 4601 ] 016000391 - e - 0 1 - 2 - 201 6 / 12 digital interface: - digital input port: max 20 ch (16ch x 1 port , 2ch x 2port ) when tdm mode - digital output port: max 20 ch ( 16ch x 1 port , 2ch x 2port ) when tdm mod e - independent lrck/bick input port x 2 lines - data format: msb 32,24 - bit / lsb 24,20,16 - bit / i 2 s - pcm short / long frame supported - tdm format supported digital mixer circuit independent digital volume (+12 to - 115db, 0.5db step, mute) pll circuit p interface: spi(7mhz max), i 2 c - bus ( max 1mhz, fast mode plus) power supply: - analog avdd: 3.0 to 3.6v (typ. 3.3v) - digital lvdd: 3.0 to 3.6 v (typ. 3.3v) (3.3v 1.2v regulator integrated) - i/f tvdd: 1.7 to 3.6v (typ. 3.3v) operating temperature range: - 40 c to 85 c package : 48 - pin lqfp ( 7 mm x 7 m m, 0.5mm pitch)
[ak 4601 ] 016000391 - e - 0 1 - 3 - 201 6 / 12 3. table of contents 1. general description ................................ ................................ ................................ .............................. 1 2. features ................................ ................................ ................................ ................................ ................ 1 3. table of contents ................................ ................................ ................................ ................................ . 3 4. block diagram and functions ................................ ................................ ................................ .............. 4 device block diagram ................................ ................................ ................................ ....................... 4 5. pin configuration and functions ................................ ................................ ................................ .......... 5 pin layout ................................ ................................ ................................ ................................ ......... 5 pin functions ................................ ................................ ................................ ................................ ..... 6 handling of unused pins ................................ ................................ ................................ ................... 8 pull - down pin statuses ................................ ................................ ................................ ..................... 9 power - down status of output pins ................................ ................................ ................................ . 10 6. absolute maximum ratings ................................ ................................ ................................ ................ 11 7. recommended operating conditions ................................ ................................ ................................ 11 8. electrical characteristics ................................ ................................ ................................ .................... 12 analog characteristics ................................ ................................ ................................ .................... 12 power consumption ................................ ................................ ................................ ........................ 18 9. digital filter characteristics ................................ ................................ ................................ ................ 19 10. dc characteristics ................................ ................................ ................................ .............................. 27 dc characteristics ................................ ................................ ................................ .......................... 27 11. switching characteristics ................................ ................................ ................................ ................... 28 12. fun ctional descriptions ................................ ................................ ................................ ...................... 35 system clock ................................ ................................ ................................ ................................ .. 35 data path setting ................................ ................................ ................................ ............................ 45 power - up sequence ................................ ................................ ................................ ........................ 64 ldo (internal circuit drive regulator) ................................ ................................ ............................ 65 power - down and reset ................................ ................................ ................................ ................... 65 sto bit status ................................ ................................ ................................ ................................ . 67 p interface setting and pin status ................................ ................................ ................................ 67 i 2 c bus interface (csn = h) ................................ ................................ ................................ ......... 69 mixer ................................ ................................ ................................ ................................ ................ 73 vol ................................ ................................ ................................ ................................ ................... 74 analog input blcok ................................ ................................ ................................ .......................... 76 adc block (adc1, adc2, adcm) ................................ ................................ ................................ . 78 dac block (dac1, dac2 and dac3 ) ................................ ................................ ............................ 82 register map ................................ ................................ ................................ ................................ ... 86 register definitions ................................ ................................ ................................ ......................... 89 13. recommended external circuits ................................ ................................ ................................ ...... 104 connection diagram ................................ ................................ ................................ ..................... 104 peripheral circuit ................................ ................................ ................................ ........................... 106 14. package ................................ ................................ ................................ ................................ ............ 108 outline dimensions ................................ ................................ ................................ ....................... 108 material and lead finish ................................ ................................ ................................ ............... 108 marking ................................ ................................ ................................ ................................ .......... 109 15. ordering guide ................................ ................................ ................................ ................................ . 109 ordering guide ................................ ................................ ................................ .............................. 109 16. revision history ................................ ................................ ................................ ................................ 110
[ak 4601 ] 016000391 - e - 0 1 - 4 - 201 6 / 12 4. block diagram and functions device block diagram figure 1 . block diagram
[ak 4601 ] 016000391 - e - 0 1 - 5 - 201 6 / 12 5. pin configuration and functions pin layout pins with framed name are pulled down internally. ainmp / ainm ain5r gndin5 ain5l ain2ln / ain4l ain2lp / ain3l ain2rn / ain4r ain2rp / ain3r ain1r / inp2 inn2 ain1l / inp1 inn1 36 35 34 33 32 31 30 29 28 27 26 25 avdd ainmn 37 24 mpwr2 avdd 38 23 mpwr1 avss 39 22 mpref vcom 40 lvdd 21 testi vrefh 41 20 dvss2 vrefl 42 19 lvdd aout1r 43 18 avdrv aout1l 44 17 pdn aout2r 45 16 si / i2cfil aout2l 46 15 sclk / scl aout3r 47 14 so/sda aout3l 48 13 csn tvdd 1 2 3 4 5 6 7 8 9 10 11 12 clko bick1 lrck1 sdin1 sdout1 dvss1 tvdd sdout2 sdin2 lrck2/sdout3 bick2 / sdin3 mcki ????? *** ? 48pin lqfp ( top view ) *** input output i / o power
[ak 4601 ] 016000391 - e - 0 1 - 6 - 201 6 / 12 pin functions no. pin name i/o function 1 clko o master clock output pin 2 bick 1 i/o serial bit clock 1 pin 3 lrck 1 i/o lr channel select clock 1 pin 4 sdin1 i serial digital data input 1 pin 5 sdout 1 o serial digital data output 1 pin 6 dvss 1 - digital ground 1 pin 0v 7 tvdd - digital i/f power supply pin 1.7 ~ 3.6 v (typ. 3.3 v) 8 sdout2 o serial data output 2 pin 9 sdin2 i serial data input 2 pin 10 lrck2 i/ o lr channel select clock 2 pin (mseln bit = l , default) sdout3 serial data output 3 pin (mseln bit = h ) 11 bick2 i/o serial bit clock 2 pin (mseln bit = l , default) sdin3 serial data input 3 pin (mseln bit = h ) 12 mck i i master clock pin 13 csn i spi i/f chip select n pin during power - down state or when p i/f are not in use, 14 so o serial data output pin for spi i/f this pin outputs sda i/o serial data in/output pin for i 2 c i/f this pin outputs 15 sclk i serial data clock input pin for spi i/f scl i serial data clock input pin for i 2 c i/f 16 si i serial data input pin for spi i/f i2cfil i i 2 c i/f mode select input pin i2cfil = l: fast mode (400khz) = h: fast mode plus (1mhz) ( 17 pdn i power - down n pin use this pin to power down th e AK4601 . the pdn pin should be held l when power is supplied.
[ak 4601 ] 016000391 - e - 0 1 - 7 - 201 6 / 12 no. pin name i/o function 18 avdrv o ldo output pin connect a 2. 2uf ceramic capa citor between this pin and dvss2 . do not connect this pin to an external circuit. 19 lvdd - digital core power supply pin 3.0 ~ 3.6v (typ.3.3v) 20 dvss2 - digital ground 2 pin 0v 21 testi i test input pin it must be tied 22 mpref o ripple filter pin for microphone power supply connect a 1 uf ceramic capacitor between this pin and avss. do not connect this pin to an external circuit. 23 mpwr1 o power supply output 1 pin for microphone this pin outputs hi z durin 24 mpwr2 o power supply output 2 pin for microphone this pin outputs hi z durin 25 inn1 i mic lch inverted differential input 1 pin 26 ain 1 l i mic lch single - ended input 1 pin inp1 i mic lch non - inverted differential input 1 pin 27 inn2 i mic rch inverted differential input 2 pin 28 ain1r i mic rch single - ended input 1 pin inp2 i mic rch non - inverted differential input 2 pin 29 ain2rp i adc2 rch non - inverted differential input 2 pin ain3r i adc2 rch single - ended input 3 pin 30 ain2rn i adc2 rch inverted differential input 2 pin ain4r i adc2 rch single - ended input 4 pin 31 ain2lp i adc2 lch non - inverted differential input 2 pin ain3l i adc2 lch single - ended input 3 pin 32 ain2ln i adc2 lch inverted differential input 2 pin ain4l i adc2 lch single - ended input 4 pin 33 ain5l i adc2 lch pseudo differential input 5 pin 34 gndin5 i adc2 pseudo differential ground input 5 pin 35 ain5r i adc2 rch pseudo differential input 5 pin 36 ainmp i adcm non - inverted differential input pin ainm i adcm single - ended input pin 37 ainmn i adcm inverted differential input pin 38 avdd - analog power supply pin 3.0 ~ 3.6v (typ.3.3v) 39 avss - analog ground pin 0v 40 vcom o analog common voltage output pin connect a 2. 2uf ceramic capacitor between this pin and avss. do not connect this pin to an external circuit. this pin outputs durin
[ak 4601 ] 016000391 - e - 0 1 - 8 - 201 6 / 12 no. pin name i/o function 41 vrefh i analog high - level reference voltage input pin connect this pin to avdd. 42 vrefl i analog low - level reference voltage input pin connect this pin to avss. 43 aout1r o dac1 rch analog output pin this pin outputs hi z durin 44 aout1l o dac1 lch analog output pin this pin outputs hi z during 45 aout2r o dac 2 rch analog output pin this pin outputs hi z durin 46 aout2l o dac 2 lch analog output pin this pin outputs hi z during 47 aout 3 r o dac 3 rch analog output pin this pin outputs hi z durin 48 aout 3 l o dac 3 lch analog output pin this pin outputs hi z during handling of unused pins unused i/o pins must be connected appropriately. classification pin name setting analog mpref, mpwr1, mpwr2, ain 1 l/inp1, inn1, ain 1 r/inp2, inn2, ain2lp/ain3l, ain2ln/ain4l, ain2rp/ain3r, ain2rn/ain4r, ain5l, gndin5, ain5r, ainmp/ainm, ainmn, aout1l, aout1r aout2l, aout2r, aout 3 l, aout 3 r open digital sdout1 , sdout2, clko open bick2 / sdin3 , sdin 2 , sdin 1 , lrck1 , bick1, lrck2 /sdout3 , mcki, testi connect to dvss1 ~ 2 table 1 . handling of unused pins
[ak 4601 ] 016000391 - e - 0 1 - 9 - 201 6 / 12 pull - down pin statuses pin no. pin power - down pdn pin = l power - down release pdn pin = h ( slave mode, msnx bit = 0 ) power - down release pdn pin = h (master mode msnx bit = 1 ) pswxn bit = 1 pswxn bit = 0 1 clko pulled - down (50k) output output output 2 bick 1 pulled - down (50k) input hiz input pulled - down (46k) output 3 lrc k 1 pulled - down (50k) input hiz input pulled - down (46k) output 5 sdout 1 pulled - down (50k) output output output 8 sdout 2 pulled - down (50k) output output output 10 lrc k 2/sdout3 pulled - down (50k) - - lrc k 2 (mseln bit = l ) - input hiz input pulled - down (46k) output sdout 3 (mseln bit = h ) - output output output 11 bick 2/sdin3 pulled - down (50k) - - bick 2 (mseln bit = l ) - input hiz input pulled - down (46k) output sdin3 (mseln bit = h ) - input hiz input hiz input 18 avdrv pulled - down (70 ) output output output 2 1 testi pulled - down (25k) pulled - down (25k) pulled - down (25k) pulled - down (25k) table 2 . p ull - down pin statuses (x=1~ 2 )
[ak 4601 ] 016000391 - e - 0 1 - 10 - 201 6 / 12 power - down status of output pins no pin name i/o power - down status no pin name i/o power - down status 1 clko o l output 23 mpwr1 o hi - z output 2 bick1 i/o input 24 mpwr2 o hi - z output 3 lrck1 i/o input 40 vcom o l output 5 sdout1 o l output 43 aout1r o hi - z output 8 sdout2 o l output 44 aout1l o hi - z output 10 lrck2 / sdout3 i/o input 45 aout2r o hi - z output 11 bick2 /sdin3 i/o input 46 aout2l o hi - z output 14 so/sda i/o hi - z output 47 aout3r o hi - z output 18 avdrv o l output 48 aout3l o hi - z output 22 mpref o l output table 3 . po wer - down status of output pins
[ak 4601 ] 016000391 - e - 0 1 - 11 - 201 6 / 12 6. absolute maximum ratings (avss=dvss1=dvss2=0v ; note 1 ) parameter symbol m in . m ax . unit power supplies analog digital1(core) digital 2 (i/f) difference (avss, dvss1 ~ 2 ) ( note 1 ) avdd lvdd tvdd gnd ? ? note 2 . the maximum analog input voltage is a smaller value between (avdd+0.3)v and 4.3v. note 3 . the maximum digital input voltage of sdin1, sdin2, bick2 /sdin3 , lrck1, bick1, mcki, lrck2 /sdout3 , pdn, sclk/scl, so/sda, csn, si/i2cfil pin s is a smaller value between ( tvdd +0.3)v and 4.3v. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. 7. recommended operating conditions (avss=dvss1=dvss2=0v ; note 1 ) parameter symbol m in . t yp . m ax . unit power supplies analog digital1(core) digital 2 (i/f) difference1 difference2 avdd lvdd tvdd avdd C C l when power is supplied. the pdn pin is allowed to be h after all power supplies are applied and settled. note 5 . d o not turn off the power supply of the AK4601 wit h the power supply of the peripheral device turned on when using the i 2 c interface. pull - up resistors of sda and scl pins should be connected to tvdd or less voltage. warning: akm assumes no responsibility for the usage beyond the conditions in the datasheet.
[ak 4601 ] 016000391 - e - 0 1 - 12 - 201 6 / 12 8. electrical characteristics analog characteristics 1. mic amp gain ( ta = 25 ? c ; avdd= vrefh= lvdd = tvdd =3.3v ; avss= vrefl= dvss1=dvss2=0v , adc1vl/r bit = 0 ) mic amp parameter m in . t yp . m ax . unit input impedance 14 20 26 k 2. mic bias output ( t a= 25 ? c ; avdd= vre fh= lvdd = tvdd =3.3v ; av ss= vrefl= dv ss1=dvss2=0v ; measurement frequency = 20hz~20khz ) mic bias parameter m in . t yp . m ax . unit output voltage 2.3 2.5 2.7 v load resistance 2 k
[ak 4601 ] 016000391 - e - 0 1 - 13 - 201 6 / 12 3. mic amp + adc1 ( ta = 25 ? c ; avdd= vrefh= lvd d = tvdd =3.3v ; avss= vrefl= dvss1= dvss2 =0v ; signal frequency = 1khz; 24bit data; bick= 64fs ; measurement frequency bw=20 hz ~ 20khz @fs=48khz ; measurement frequency bw=20 hz ~ 40khz @fs=96khz ,192khz ; adc1vl/r bit = 0; mgnl/r[3:0] bits = 0h (0db) ) mic amp + adc1 parameter m in . t yp . m ax . unit resolution 24 bit differential input full - scale input voltage ( note 7 ) 2.1 2.3 2.5 vpp ( note 8 ) 0.264 0.290 0.315 ( note 9 ) 2. 55 2. 83 3.11 s/(n+d) ( - 1dbfs) fs=48khz ( note 7 ) 85 95 db fs=48khz ( note 8 ) 87 fs=96khz ( note 7 ) 92 fs=96khz ( note 8 ) 84 fs=192khz ( note 7 ) 92 fs=192khz ( note 8 ) 84 dynamic range ( - 60dbfs) fs=48khz (a - weighted) ( note 7 ) 98 106 db fs=48khz (a - weighted) ( note 8 ) 95 fs=96khz ( note 7 ) 99 fs=96khz ( note 8 ) 89 fs=192 khz ( note 7 ) 99 fs=192 khz ( note 8 ) 89 s/n fs=48khz (a - weighted) ( note 7 ) 98 106 db fs=48khz (a - weighted) ( note 8 ) 95 fs=96khz ( note 7 ) 99 fs=96khz ( note 8 ) 89 fs=192 khz ( note 7 ) 99 fs=192 khz ( note 8 ) 89 inter - channel isolation ( note 6 ) 90 105 db channel gain mismatch 0.0 0.3 db psrr ( note 7 , note 10 ) 50 db cmrr ( note 11 ) 6 0 80 db
[ak 4601 ] 016000391 - e - 0 1 - 14 - 201 6 / 12 parameter m in . t yp . m ax . unit s i ngle - ended input full - scale input voltage ( note 7 ) 2.1 2.3 2.5 vpp ( note 8 ) 0.264 0.290 0.315 ( note 9 ) 2. 55 2. 83 3.11 s/(n+d) ( - 1dbfs) fs=48khz ( note 7 ) 85 95 db fs=48khz ( note 8 ) 87 fs=96khz ( note 7 ) 92 fs=96khz ( note 8 ) 84 fs=192khz ( note 7 ) 92 fs=192 khz ( note 8 ) 84 dynamic range ( - 60dbfs) fs=48khz (a - weighted) ( note 7 ) 96 104 db fs=48khz (a - weighted) ( note 8 ) 92 fs=96khz ( note 7 ) 97 fs=96khz ( note 8 ) 86 fs=192 khz ( note 7 ) 97 fs=192 khz ( note 8 ) 86 s/n fs=48khz (a - weighted) ( note 7 ) 96 104 db fs=48khz (a - weighted) ( note 8 ) 92 fs=96khz ( note 7 ) 97 fs=96khz ( note 8 ) 86 fs=192 khz ( note 7 ) 97 fs=192 khz ( note 8 ) 86 inter - channel isolation ( note 6 ) 90 105 db channel gain mismatch 0.0 0.3 db psrr ( note 7 , note 10 ) 50 db note 6 . inter - channel isolation with - 1dbfs signal input between lch and rch. note 7 . adc1vl/r bit = 0 , mgnl/r[3:0] bits = 0h (0db) . input full - scale voltage is propotional to avdd (0.7 x avdd). note 8 . adc1vl/r bit = 0 , mgnl/r[3:0] bits = 9h (+18db) . input full - scale voltage is propotional to avdd (0.088 x avdd). note 9 . adc1vl/r bit = 1 , mgnl/r[3:0] bits = 0h (0db) . input full - scale voltage is propotional to avdd (0.86 x avdd). note 10 . psr r is applied to avdd and vrefh with 1khz, 50 mvpp. note 11 . common mode rejection ratio is applied 1khz and 100mvpp sine waves to both differential input pins. it is defined as a reference value when appling 1khz and 100mvpp sine waves to the differential input.
[ak 4601 ] 016000391 - e - 0 1 - 15 - 201 6 / 12 4. adc2 (ta = 25 ? c ; avdd= vrefh= lvdd = tvdd =3.3v; avss= vrefl= dvss1= dvss2=0v ; signal frequency =1khz; 24bit data; bick=64fs; measurement frequency bw=20hz ~ 20khz @fs=48khz ; measurement frequency bw=20hz ~ 40khz @fs=96khz,192khz ; adc2vl/r bit =0 ) adc2 parameter m in . t yp . m ax . unit resolution 24 bit input impedance 14 20 26 k 0 . input full - scale voltage is propotional to avdd (0.7 x avdd). note 14 . adc2vl/r bit = 0 . input full - scale voltage is propotional to avdd (0.86 x avdd). note 15 . ain 3 l, ain 3 r, ain 4 l, ain 4 r , ain5l and ain5r pins. note 16 . common mode rejection ratio is applied 1khz and 100mvpp sine waves to both pseudo - differential input and pseudo - differential ground input pins. it is defined as a reference value when appling 100mvpp sine wave to the pseudo - differential input.
[ak 4601 ] 016000391 - e - 0 1 - 16 - 201 6 / 12 5. adc m (ta= 25 ? c ; a vdd= vrefh= lvdd = tvdd =3.3v; avss= vrefl= dvss1=dvss2=0v ; signal frequency =1khz; 24bit data; bick=64fs; measurement frequency bw=20hz ~ 20khz @fs=48khz ; measurement frequency bw=20hz ~ 40khz @fs=96khz,192khz ; adcmv bit =0 ) adcm parameter m in . t yp . m ax . unit resolution 24 bit input impedance 14 20 26 k 0 . input full - scale voltage is propotional to avdd (0.7 x avdd). note 19 . adcmv bit = 1 . input full - scale voltage is propotional to avdd (0.86 x avdd). note 20 . ainm pin
[ak 4601 ] 016000391 - e - 0 1 - 17 - 201 6 / 12 6 . dac (ta= 25 ? c ; a vdd= vrefh= lvd d = tvdd = 3.3v; avs s= vrefl= dvss1= dvss2=0v ; signalfrequency =1khz; 32 bit data; bick= 64fs; measurement frequency bw=20 hz ~ 20khz @ fs=48khz ; measurement frequency bw=20 hz ~ 40khz @ fs=96khz ,192khz ) dac1 dac2 dac3 parameter m in . t yp . m ax . unit resolution 32 bit output voltage ( note 21 ) 2.55 2.83 3.11 vpp s/(n+d) (0dbfs) fs=48khz 80 91 db fs=96khz 89 fs=192khz 89 dynamic range ( - 60dbfs) fs=48khz (a - weighted) 100 108 db fs=96khz 101 fs=192khz 101 s/n fs=48khz (a - weighted) 100 108 db fs=96khz 101 fs=192khz 101 inter - channel isolation (fin=1khz) ( note 22 ) 90 110 db channel gain mismatch 0.0 0.7 db load resistance ( note 23 ) 10 k note 22 . inter - channel isolation between each dac of lch and rch with 0dbfs si gnal input. (aout1l and aout1r, aout2l and aout2r and aout3l and aout3 r) note 23 . to ac load.
[ak 4601 ] 016000391 - e - 0 1 - 18 - 201 6 / 12 power consumption (ta=25 ? c ; avdd =vrefh =3.0~3.6v(typ=3.3v, max=3.6v); lvdd =3.0~3.6v(typ=3.3v, max=3.6v); tvdd = 1.7 ~ 3.6 v(typ= 3.3 v, max= 3.6 v); avss= vrefl= dvss1=dvss2=0v ) parameter symbol m in . t yp . m ax . unit operation current consumption ( note 24 ) (pdn pin= h) (pdn pin= l)
[ak 4601 ] 016000391 - e - 0 1 - 19 - 201 6 / 12 9. digital filter characteristics 1. adc block (ta= 25 ? c ; avdd = vrefh =3.0~3.6v; lvdd =3.0~ 3.6v; tvdd = 1.7 ~ 3.6 v; avss =vrefl =dvss1 =dvss2 =0v) 1 - 1 sharp roll - off filter ( ad sd bit = 0, ad sl bit = 0) fs=48khz parameter symbol m in . t yp . m ax . unit sharp roll - off passband ( note 25 ) 0db/ - 0.06 db pb 0 - 22.1 khz - 3 .0db pb - 2 3.7 - khz stopband ( note 25 ) sb 27.8 - - khz stopband attenuation sa 85 - - db group delay distortion : 0 hz ~20khz ? parameter symbol m in . t yp . m ax . unit sharp roll - off passband ( note 25 ) 0db/ - 0.06db pb 0 - 44.2 khz - 3 .0db pb - 4 7.5 - khz stopband ( note 25 ) sb 55.6 - - khz stopband attenuation sa 85 - - db group delay distortion : 0 hz ~40khz ? parameter symbol m in . t yp . m ax . unit sharp roll - off passband ( note 25 ) 0db/ - 0.04 db pb 0 - 83.7 khz - 3 .0db pb - 96.0 - khz stopband ( note 25 ) sb 122.9 - - khz stopband attenuation sa 85 - - db group delay distortion : 0 hz ~40khz ?
[ak 4601 ] 016000391 - e - 0 1 - 20 - 201 6 / 12 1 - 2 slow roll - off filter ( ad sd bit = 0, ad sl bit = 1) fs=48khz parameter symbol m in . t yp . m ax . unit slow roll - off passband ( note 25 ) 0db/ - 0.074 db pb 0 - 12.5 khz - 3 .0db - 19.2 - khz stopband ( note 25 ) sb 36.5 - - khz stopband attenuation sa 85 - - db group delay distortion : 0 hz ~20khz ? parameter symbol m in . t yp . m ax . unit slow roll - off passband ( note 25 ) 0db/ - 0.074 db pb 0 - 25 khz - 3 .0db - 38.5 - khz stopband ( note 25 ) sb 73 - - khz stopband attenuation sa 85 - - db group delay distortion : 0 hz ~40khz ? parameter symbol m in . t yp . m ax . unit slow roll - off passband ( note 25 ) 0db/ - 0. 1 db pb 0 - 31.1 khz - 3 .0db - 62.3 - khz stopband ( note 25 ) sb 14 5.9 - - khz stopband attenuation sa 85 - - db group delay distortion : 0 hz ~40khz ?
[ak 4601 ] 016000391 - e - 0 1 - 21 - 201 6 / 12 1 - 3 short delay sharp roll - off filter ( ad sd bit = 1, ad sl bit = 0) fs=48khz parameter symbol m in . t yp . m ax . unit short delay sharp roll - off passband ( note 25 ) 0db/ - 0.06 db pb 0 - 22.1 khz - 3 .0db - 2 3.7 - khz stopband ( note 25 ) sb 27.8 - - khz stopband attenuation sa 85 - - db group delay distortion : 0 hz ~ 2 0khz ? parameter symbol m in . t yp . m ax . unit short delay sharp roll - off passband ( note 25 ) 0db/ - 0.06 db pb 0 - 44.2 khz - 3 .0db - 47.5 - khz stopband ( note 25 ) sb 55.6 - - khz stopband attenuation sa 85 - - db group delay distortion : 0 hz ~40khz ? parameter symbol m in . t yp . m ax . unit short delay sharp roll - off passband ( note 25 ) 0db/ - 0.04 db pb 0 - 83.7 khz - 3 .0db - 96.0 - khz stopband ( note 25 ) sb 122.9 - - khz stopband attenuation sa 85 - - db group delay distortion : 0 hz ~40khz ?
[ak 4601 ] 016000391 - e - 0 1 - 22 - 201 6 / 12 1 - 4 short delay slow roll - off filter ( ad sd bit = 1, ad sl bit = 1) fs=48khz parameter symbol m in . t yp . m ax . unit short delay slow roll - off passband ( note 25 ) 0db/ - 0.074 db pb 0 - 12.5 khz - 3 .0db - 19.2 - khz stopband ( note 25 ) sb 3 6.5 - - khz stopband attenuation sa 85 - - db group delay distortion : 0 hz ~ 2 0khz ? parameter symbol m in . t yp . m ax . unit short delay slow roll - off passband ( note 25 ) 0db/ - 0.074 db pb 0 - 25 khz - 3 .0db - 38.5 - khz stopband ( note 25 ) sb 73 - - khz stopband attenuation sa 85 - - db group delay distortion : 0 hz ~40khz ? parameter symbol m in . t yp . m ax . unit short delay slow roll - off passband ( note 25 ) 0 db/ - 0. 1 db pb 0 - 31.1 khz - 3 .0db - 63.2 - khz stopband ( note 25 ) sb 145.9 - - khz stopband attenuation sa 85 - - db group delay distortion : 0 hz ~40khz ? note 26 . d elay time caused by the digital filter calculation. this time is measured from an impulse signal input until impulse data are set into the output register. it includes group delay by hpf .
[ak 4601 ] 016000391 - e - 0 1 - 23 - 201 6 / 12 2. dac block (ta= 25 ? c ; avdd = vrefh= 3.0~3.6v; lvdd =3.0~3.6v; tvdd = 1.7 ~ 3.6 v; avss= vrefl= dvss1= dvss2=0v ) 2 - 1 sharp roll - off filter (dasd bit = 0, dasl bit = 0) fs= 4 8 khz parameter symbol m in . t yp . m ax . unit sharp roll - off passband ( note 27 ) ? ? digital filter + sc f + smf ( note 30 ) frequency response : 0 ? parameter symbol m in . t yp . m ax . unit sharp roll - off passband ( note 27 ) ? ? digital filter + scf + smf ( note 30 ) frequency response : 0 ? parameter symbol m in . t yp . m ax . unit sharp roll - off passband ( note 27 ) ? ? digital filter + scf + smf ( note 30 ) frequency response : 0 ? pb=0.4535 ? fs, sb=0.546 ? fs note 28 . pass - band gain amplitude of double seep over sampling filter at the first step of interpolator . note 29 . d elay time caused by the digital filter calculation. this time is measured from setting of the 16/20/24/32 - bit impulse data to the input registers to output of the analog peak signal. note 30 . the output level with a 1khz , 0db sine wave input is defined as 0db. note 31 . band width of stopband attenuation ranges from 0khz to fs.
[ak 4601 ] 016000391 - e - 0 1 - 24 - 201 6 / 12 2 - 2 slow roll - off filter (dasd bit = 0, dasl bit = 1) fs= 4 8 khz parameter symbol m in . t yp . m ax . unit s low roll - off passband ( note 32 ) ? ? digital filter + sc f + smf ( note 30 ) frequency response : 0 ? parameter symbol m in . t yp . m ax . unit s low roll - off passband ( note 32 ) ? ? digital filter + sc f + smf ( note 30 ) frequency response : 0 ? parameter symbol m in . t yp . m ax . unit s low roll - off passband ( note 32 ) ? ? digital filter + sc f + smf ( note 30 ) frequency response : 0 ? pb=0. 185 ? fs, sb= 0. 888 ? fs
[ak 4601 ] 016000391 - e - 0 1 - 25 - 201 6 / 12 2 - 3 short delay sharp roll - off filter (dasd bit = 1, dasl bit = 0) fs = 48 khz parameter symbol m in . t yp . m ax . unit s hort delay sharp roll - off passband ( note 27 ) ? ? digital filter + sc f + smf ( note 30 ) frequency response : 0 ? parameter symbol m in . t yp . m ax . unit s hort delay sharp roll - off passband ( note 27 ) ? ? digital filter + s cf + smf ( note 30 ) frequency response: 0 ? parameter symbol m in . t yp . m ax . unit s hort delay sharp roll - off passband ( note 27 ) ? ? digital filter + sc f + smf ( note 30 ) frequency response : 0 ?
[ak 4601 ] 016000391 - e - 0 1 - 26 - 201 6 / 12 9.4 short delay slow roll - off filter (dasd bit = 1, dasl bit = 1) fs= 48 khz parameter symbol m in . t yp . m ax . unit s hort delay slow roll - off passband ( note 33 ) ? ? digital filter + sc f + smf ( note 30 ) frequency response : 0 ? parameter symbol m in . t yp . m ax . unit s hort delay slow roll - off passband ( note 33 ) ? ? digital filter + sc f + smf ( note 30 ) frequency response : 0 ? parameter symbol m in . t yp . m ax . unit s hort delay slow roll - off passband ( note 33 ) ? ? digital filter + sc f + smf ( note 30 ) frequency response : 0 ? pb=0. 252 ? fs, sb= 0. 864 ? fs
[ak 4601 ] 016000391 - e - 0 1 - 27 - 201 6 / 12 10. dc characteristics dc characteristics ( ta= - 40~8 5 ? c ; avd d= vrefh= 3.0~3.6v; lvdd =3.0~3.6v; tvdd = 1.7 ~ 3.6 v; avss= vrefl= dvss1= dvss 2=0v ) parameter symbol min. typ. max. unit high - level input voltage 1 ( note 34 ) vih1 80% tvdd v low - level input voltage 1 ( note 34 ) vil1 20% tvdd v high - level input voltage 2 ( note 35 ) vih 2 70% tvdd v low - level input voltage 2 ( note 35 ) vil 2 30% tvdd v high - level output voltage iout= - 100 ? ? < 2.0v (iout=3ma) vol 2 20%tvdd v input leak current ( note 36 ) iin 10 ?
[ak 4601 ] 016000391 - e - 0 1 - 28 - 201 6 / 12 11. switching characteristics 1. system clock ( ta= - 40~8 5 ? c ; avd d = vrefh =3.0~3.6v; lvdd =3.0~3.6v; tvdd = 1.7 ~ 3.6 v ; avss= vrefl= dv ss1= dvss2=0v ; cl=20pf) parameter symbol min. typ. max. unit mcki input timing duty cycle duty 40 50 60 % input frequency f clk 0.256 24.576 mhz clko output timing output frequency fclko 2.048 24.576 mhz duty cycle dclko 50 % lrck/bick input timing (slave mode) lrck input timing frequency fs 8 192 khz bick input timing frequency ( note 37 ) fbc l k 0.256 24.576 mhz pulse width low tbc l kl 0.4 / fbclk ns pulse width high tbc l kh 0.4 / fbclk ns lrck/bick output timing (master mode) lrck output timing frequency fs 8 192 khz pulse width high pcm short/long frame i 2 s/dsp mode tlrckh tlrckh 1/fbc l k 50 ns % bick output timing frequency ( note 37 ) fbc l k 0.256 24.576 mhz duty dbc l k 50 % note 37 . required to meet the following expression: fbc l k 2 x fs x ( input/output data length )
[ak 4601 ] 016000391 - e - 0 1 - 29 - 201 6 / 12 figure 2 . system clock timing 2 . power down ( ta= - 40~8 5 ? c ; a vdd= vrefh= 3.0~3.6v; lvdd =3.0~3.6v ; tvdd = 1.7 ~ 3.6 v ; avss= vrefl= dvss1= dvs s2=0v ) parameter symbol min . t yp . m ax . unit pdn pulse width ( note 38 ) trst 600 ns note 38 . the pdn pin must be l when power up the AK4601 . figure 3 . reset timing 1/f clk 1/f clk vih 1 vil 1 mck i 1/fs 1/fs tbclkl tbclkh 1/fbclk 1/fbclk vih 1 vi l1 lrck bick vih 1 vi l1 vil 1 trst pdn
[ak 4601 ] 016000391 - e - 0 1 - 30 - 201 6 / 12 3. serial data interface (sdin x , sdout x ) ( ta= - 40~8 5 ? c ; avdd= vrefh= 3.0~3.6v; lvdd =3.0~3.6v; tvdd = 1.7 ~ 3.6 v; avss= vrefl= dvss1= dvss2=0v; cl=20pf) parameter symbol m in . t yp . m ax . unit slave mode delay time from bick bick delay time from bick to serial data output master mode bick frequency fbclk 32, 48, 64, 128, 256 , 512 fs bick duty cycle duty 50 % delay time from bick when the bick polarity is inverted by setting bckpx bit = 1 . note 40 . it is measured from bick when the bick polarity is inverted by setting bckpx bit = 1 . note 41 . set sdophx bit to 1 and the data from sdoutx pin should be output based on bick when bickx speed is more than 12.288mhz such as tdm512 mode with 48khz sampling frequency , tdm256 mode with 96khz sampling frequency or tdm128 mode with 192khz sampling frequency in slave mode. sdophx bit must be set to 0 in master mode.
[ak 4601 ] 016000391 - e - 0 1 - 31 - 201 6 / 12 3 - 1. slave mode figure 4 . serial interface input timing in slave mode figure 5 . serial interface output timing in slave mode (sdophx bit = 0 ) figure 6 . serial interface output timing in slave mode (sdophx bit = 1 ) tbsids tblrd tlrbd d vih 1 d vil 1 d tbsidh sdin x lrck(i) bick(i) vih 1 d vil 1 d vih 1 d vil 1 d vih 1 lrck (i) bick (i) vil 1 sdout x 50% t vdd tbsod 1 d vih 1 vil 1 tblrd tlrbd d tbsod1 d vih 1 lrck (i) bick (i) vil 1 sdout x 50% t vdd tbsod 2 d vih 1 vil 1 tblrd tlrbd d tbsod2 d
[ak 4601 ] 016000391 - e - 0 1 - 32 - 201 6 / 12 3 - 2. master mode figure 7 . serial interface input timing in master mode figure 8 . serial interface output timing in master mode 4 . spi interface ( ta= - 40~8 5 ? c ; avdd = vrefh= 3.0~3.6v; lvdd =3.0~3.6v; tvdd = 1.7 ~ 3.6 v; avss= vrefl= dvss1= dvss2=0v ; cl=20pf) parameter symbol m in . t yp . m ax . unit p interface signal sclk frequency fsclk 7 mhz sclk low - level width tsclkl 60 ns sclk high - level width tsclkh 60 ns microcontroller AK4601 csn high - level width twrqh 150 ns from csn pdn pdn csn csn sclk sclk csn AK4601 microcontroller delay time from sclk tbsids tmbl tmbl d lrck (o) bick(o) vih 1 d vil 1 tbsidh sdin x 5 0%tvdd 5 0%tvdd tbsod d lrck (o) bi ck (o) sdout x 50%tvdd 50%tvdd 50%tvdd tbsod d
[ak 4601 ] 016000391 - e - 0 1 - 33 - 201 6 / 12 figure 9 . spi interface timing1 figure 10 . spi interface timing 2 (microcontroller AK4601 ) figure 11 . spi interface timing 3 ( AK4601 microcontroller) tsclkh tsclkl 1/fsclk 1/fsclk sclk vih 1 vil 1 vih 1 vil 1 vih 1 vil 1 trst pd n csn tirrq twrqh tsis tsih tscw tscw twsc tscw cs n si vih 1 vil 1 vih 1 twsc sclk vil 1 vih 1 vil 1 tsos tsoh sclk vil 2 vih 2 so vih 2 vil 2
[ak 4601 ] 016000391 - e - 0 1 - 34 - 201 6 / 12 5 . i 2 c interface ( ta= - 40~8 5 ? c ; avdd =vrefh =3.0~3.6v; lvdd =3.0~3.6v; tvdd = 1.7 ~ 3.6 v; avss= vrefl= dvss1 =dvss2=0v ) parameter symbol m in . t yp . m ax . unit i 2 c timing scl clock frequency fscl 400 khz bus free time between transmissions tbuf 1.3 ? ? ? ? ? ? ? ? ? ? 2 c: fast mode plus> parameter symbol m in . t yp . m ax . unit i 2 c timing scl clock frequency fscl 1 mhz bus free time between transmissions tbuf 0.5 ? ? ? ? ? ? ? ? ? ? figure 12 . i 2 c bus interface timing thigh scl sda vih 2 tlow tbuf thd:sta t r tf thd:dat tsu:dat tsu:sta stop start start stop tsu:sto vil 2 vih 2 vil 2 tsp
[ak 4601 ] 016000391 - e - 0 1 - 35 - 201 6 / 12 12. functional descriptions system clock 1 . clock mode th e AK4601 has a pll circuit to generate an internal operation clock. an input pin for the pll reference clock is selected by ref sel[ 2 : 0] bits ( table 4 ) . refmode[4:0] bits set the frequency of the reference clock ( table 5 ) . a reference clock input pin and the reference clock frequency must be changed during clock reset. refsel[ 2 :0] bits reference clock 000 mcki pin (default) 001 bick 1 pin 010 bick 2 pin others n/a table 4 . pll reference clock frequency setting refmode [4:0] bits input frequency (khz) 48khz base 44.1khz base 00000 256 235.2 (default) 00001 384 352.8 00010 512 470.4 00011 768 705.6 00100 1,024 940.8 00101 1,152 1,058.4 00110 1,536 1,411.2 00111 2,048 1,881.6 01000 2,304 2,116.8 01001 3,072 2,822.4 01010 4,096 3,763.2 01011 4,608 4,233.6 01100 6,144 5,644.8 01101 8,192 7,526.4 01110 9,216 8,467.2 01111 12,288 11,289.6 10000 18,432 16,934 . 4 10001 24,576 22,579.2 others n/a n/a table 5 . reference clock frequency setting the pll block multiplies a input clock which is set by refmode[4:0] bits directly and generates a 122.88mhz/112.896mhz master clock (pll_mclk) for internal operation ( table 6 ). master clock (pll_mclk) 48khz base 44.1khz base 122.88mhz 112.896mhz table 6 . internal operation master clock a stable bick is required when using clock input from bickx (x=1~ 2 ) pin as reference clock . a clock with two different frequencies cannot be used. t he mcki pin must be put to l (dvss1) if the system does not need the mcki pin.
[ak 4601 ] 016000391 - e - 0 1 - 36 - 201 6 / 12 2 . audio h ub 2 - 1 audio hub audio hub provides simultaneous data trans mit ting and flexible path configuration for various audio sources by setting sample rate converters, input/output port that supports tdm mode and registers. therefore the AK4601 is able to support to various use cases of car - audio systems. figure 13 shows an example of when using audio play - back and hands - free talk at the same time in a car audio system. with the ak7707, akm s multi - core dsp, t he AK4601 realizes simultaneous processing of data in different sampling rates such as microphone input adc data and radio tuner audio data. figure 13 . audio h ub example
[ak 4601 ] 016000391 - e - 0 1 - 37 - 201 6 / 12 2 - 2 . clock sync domain the AK4601 has two c lock s ync d omain s (sd1 - 2 ) . r eference clock s ( lrcksdx, bicksdx, x=1~ 2 ) are output according to each register settings for sd1 - 2 ( figure 14 ). the internal audio data an d input/output data of the AK4601 mus t be synchronized with one of thes e two cloc k sync domains. when msnx bit = 0 , input pins (lrckx pin/bickx pin) are selected for the clock sync reference clock. when msnx bit = 1 , internal di viding clocks (mlrckx/mbickx) are selected for the clock sync reference clock ( table 7 ). msnx bit reference c l ock (lrcksdx/bick sdx) 0 input pin (lrckx pin/bickx pin) 1 internal di viding clock (mlrckx/mbickx) reference clock is generated internally by cksx [ 2 :0], bdvx [ 8 :0] and sdvx[2:0] bits settings. table 7 . reference clock of clock sync domain figure 14 . clock sync domain div bdv 1 [ 8 :0] s dv 1 [2 :0] mlrck 1 mbick 1 pll _ mclk mck i b ick1~2 msn 1 lr ck_sd2 bi ck_sd2 cks 2 [ 2 :0] / bdv 2 [ 8 :0] / s dv 2 [ 2 :0] bi ck2 pin lr ck2 pin msn2 div cks 1 [2:0] bi ck_sd 1 lr ck_sd 1 bi ck 1 pin lr ck 1 pin
[ak 4601 ] 016000391 - e - 0 1 - 38 - 201 6 / 12 the cl ock source of internal di viding clock mbickx is sel ected by cksx[ 2 :0] bits ( table 8 ) . mbickx is generated by di viding the selected clock source according to the bdvx[ 8 :0] bits setting ( table 9 ) . additio nally, mlrckx is generated by di viding this mbickx by setting sdvx[2:0] bits ( table 8 ) . cksx[ 2 :0] bits clock source 000 tielow (default) 001 pll mclk 010 mck i 011 bick1 100 bick2 others n/a table 8 . clock source of internal dividing clock bdvx[ 8 :0] bits divide by 0x00 1 (default) 0x01 C sdvx[2:0] bits di vide by 000 64 (default) 001 48 010 32 011 128 100 256 101 n/a 110 n/a 111 512 table 10 . m lrckx setting (n/a: not available) clock sync domain settings when pll mclk is selected as the clock source are shown in table 11 . pll mclk = 122.88mhz (48khz base ) / 112.896mhz (44.1khz base ) mbickx = pll mclk d vided by bdvx[8 :0] bits setting mlrckx = mbickx di vided by sdvx[ 2 :0] bits setting e .g. ) mbickx= 122.88mhz/240= 0.512mhz, mlrckx= 0.512mhz/64= 8khz when pll_mclk = 122.88mhz ( fs= 48khz), bdvx[8 :0] bits= 0xef ( di vide by 240) and sdvx[2:0] bits = 000 ( di vide by 64) .
[ak 4601 ] 016000391 - e - 0 1 - 39 - 201 6 / 12 when pll_mclk is selected as the clock source, frequency settings other than shown in table 11 are not available. bdvx[ 8 :0] bits bdvx[ 8 :0] bits di viding mbickx(mhz) sdvx[2:0] bits sdvx[2:0] bits di viding mlrckx(khz) 48khz base 44.1khz base 48khz base 44.1khz base 0x1df 480 0.256 0.2352 010 32 8 - 0x13f 320 0.384 0.3528 001 48 8 - 0x 0 ef 240 0.512 0.4704 000 64 8 - 0x 0 77 120 1.024 0.9408 011 128 8 - 0x 0 3b 60 2.048 1.8816 100 256 8 - 0x 0 1d 30 4.096 3.7632 111 512 8 - 0x13f 320 0.384 0.3528 010 32 12 11.025 0x 0 9f 160 0.768 0.7056 000 64 12 11.025 0x 0 4f 80 1.536 1.4112 011 128 12 11.025 0x 0 27 40 3.072 2.8224 100 256 12 11.025 0x 0 13 20 6.144 5.6448 111 512 12 11.025 0x 0 ef 240 0.512 0.4704 010 32 16 14.7 0x 0 9f 160 0.768 0.7056 001 48 16 14.7 0x 0 77 120 1.024 0.9408 000 64 16 14.7 0x 0 3b 60 2.048 1.8816 011 128 16 14.7 0x 0 1d 30 4.096 3.7632 100 256 16 14.7 0x 0 0e 15 8.192 7.5264 111 512 16 14.7 0x 0 9f 160 0.768 0.7056 010 32 24 22.05 0 0x 0 4f 80 1.536 1.4112 000 64 24 22.05 0 0x 0 27 40 3.072 2.8224 011 128 24 22.05 0 0x 0 13 20 6.144 5.6448 100 256 24 22.05 0 0x 0 09 10 12.288 11.2896 111 512 24 22.05 0 0x 0 77 120 1.024 0.9408 010 32 32 29.4 0x 0 4f 80 1.536 1.4112 001 48 32 29.4 0x 0 3b 60 2.048 1.8816 000 64 32 29.4 0x 0 1d 30 4.096 3.7632 011 128 32 29.4 0x 0 0e 15 8.192 7.5264 100 256 32 29.4 0x 0 4f 80 1.536 1.4112 010 32 48 44.1 0x 0 27 40 3.072 2.8224 000 64 48 44.1 0x 0 13 20 6.144 5.6448 011 128 48 44.1 0x 0 09 10 12.288 11.2896 100 256 48 44.1 0x 0 04 5 24.576 22.5792 111 512 48 44.1 0x 0 27 40 3.072 2.8224 010 32 96 88.2 0x 0 13 20 6.144 5.6448 000 64 96 88.2 0x 0 09 10 12.288 11.2896 011 128 96 88.2 0x 0 04 5 24.576 22.5792 100 256 96 88.2 0x 0 13 20 6.144 5.6448 010 32 192 176.4 0x009 10 12.288 11.2896 000 64 192 176.4 0x 004 5 24.576 22.5792 011 128 192 176.4 table 11 . clock sync domain setting when pll mclk is clock source for clock sync domain, set bdvx[ 8 :0] bits and sdvx[2:0] bits according to the input clock frequency when the mcki or bick pin input is selected as the clock source, as well as the pll mclk. mbickx= mcki pin or bickx pin frequency di vided by bdvx[ 8 :0] bits setting mlrckx= mbickx di vided by sdvx[ 2 :0] bits setting
[ak 4601 ] 016000391 - e - 0 1 - 40 - 201 6 / 12 2 - 3. sampling frequency setting of adc , dac blocks the adc, dac blocks of th e AK4601 a re operated by a master clock generated by dividing pll mclk. sampling frequencies of the adc1 , and the adc2 , adcm, dac1, dac2 and dac3 (hereinafter called codec) are set by fsmode[4:0] bits ( table 12 ). mode fsmode[ 4 :0] bits adc2, adcm dac1, dac2, dac3 adc1 0 00000 8khz 8khz (default) 1 00001 12khz 12khz 2 00010 16khz 16khz 3 00011 24khz 24khz 4 00100 32khz 32khz 5 00101 32khz 16 khz 6 00110 32khz 8 khz 7 00111 48khz 48khz 8 01000 48khz 24 khz 9 01001 48khz 16 khz 10 01010 48khz 8 khz 11 01011 96khz 96khz 12 01100 96khz 48 khz 13 01101 96khz 32 khz 14 01110 96khz 24 khz 15 01111 96khz 16 khz 16 10000 96khz 8 khz 17 10001 192khz 192khz 18 10010 192khz 96 khz 19 10011 192khz 48 khz 20 10100 192khz 3 2khz 21 10101 192khz 16 khz table 12 . sampling frequency settings of internal blocks (fs=48khz base ) clock sync domain of the adc1 (sdadc1) is selected by sdadc1[2:0] bits and clock sync domain of the codec (sdcodec) is selected by sdcodec[2:0] bits ( figure 20 ) . sdadc1 and sdcodec must be synchronized with pll mclk. the sampling frequency of lrck sdx for sdadc1 and the sampling frequency of the adc1 should be the same. the sampling frequency of lrck sdx for sdcodec and the sampling frequency of the code c should also be the same. set sdadc1[2:0] bits = 000 (reference c l ocks are low) when not using the adc1. in the same manner, sdcodec[2:0] bits must be set to 00 0 (reference c l ocks are low) when not using the codec.
[ak 4601 ] 016000391 - e - 0 1 - 41 - 201 6 / 12 e.g.) i nput p in is s elected for pll reference clock. ? pll setting refsel[ 2 : 0] bits = 010 (pll reference clock is set to bick2 pin=3.072mhz) ? clock sync domain setting sdadc1[2:0] bits = 001 , sdcodec[2:0] bits = 002 , msn1 bit = msn2 bit = 0 , bi ck_sd1 = bick1 pin = 64fs (0.512mhz) , lrck_sd1 = lrck1 pin = 8khz bick_sd2 = bick2 pin = 64fs (3.072mhz),lrck_sd2 = lrck2 pin = 48khz ? adc1 and codec setting fsmode[4:0] bits= 01010 ( set fs = 8khz for adc1, set codec , fs = 48khz) figure 15 . adc, dac setting example (msnx bit = 0 : input p in is s elected as pll reference clock ) note 42 . bick1/lrck1 and bick2/lrck2 must be synchronized. p ll _ mclk =122.88mhz msn 1 = 0 lr ck_sd 1 (fs=8khz) bi ck_sd 1 (64fs) internal dividing clock bi ck1 pin(64fs) lr ck 1 pin( fs=8khz) sdout1 5 adc2,m adc2,m dac 1 - 3 sdout1 5 dac 1 - 3 pll divide data bus msn2= 0 lr ck_sd2 (fs=48khz) bi ck_sd2 (64fs) b ick2 pin(64fs) l rck2 pin(fs=48khz) mlrck1 mbick1 internal dividing clock mlrck2 mbick2 sdout1 5 adc 1 adc 1 data bus divide fs=48khz f s= 8khz fs mode 1[4:0] bits= 0 1 0 1 0 fs=8khz fs mode [4:0] bits= 0 101 0 fs=48khz bick 2 pin= 3.072m hz
[ak 4601 ] 016000391 - e - 0 1 - 42 - 201 6 / 12 e.g. ) internal di viding clock is selected as pll reference clock ? pll setting refsel[ 2 :0] bits = 000 (pll reference clock is mcki pin = 3.072mhz) , pll mclk = 122.88mhz ? clock sync domain setting sdadc[2:0] bits = 001 , sdcodec[2:0] bits = 002 , msn1 bit = msn2 bit = 1 , cks1[ 2 :0] = 001 ( pll mclk is set as the reference clock of clock sync domain 1) bdv1[8:0] = 0x0ef (bick sd1 = mbick1 = 122.88mhz/240 = 0.512mhz) sdv1[2:0] = 000 (lrck sd1 = mlrck1 = 0.512mhz/64 = 8khz) cks2[ 2 :0] = 001 ( pll mclk is set as the reference clock of clock sync domain 2) bdv2[8:0] = 0x027 (bick sd2 = mbick2 = 122.88mhz/40 = 3.072mhz) sdv2[2:0] = 000 (lrck sd2 = mlrck2 = 3.072mhz/64 = 48khz) ? adc1 and codec setting fsmode[4:0] bits= 01010 (set fs = 8khz for adc1, set codec, fs = 48khz) figure 16 . adc, dac , setting example (msnx bit = 1 : internal dividing clock is selected as pll reference clock ) msn 1 = 1 lr ck_sd 1 (fs=8khz) bi ck_sd 1 (64fs) internal dividing clock bi ck1 pin(64fs) lr ck 1 pin( fs=8khz) adc2,m dac 1 - 3 sdout1 5 dac 1 - 3 pll divide data bus msn2= 1 lr ck_sd2 (fs=48khz) bi ck_sd2 (64fs) b ick2 pin(64fs) l rck2 pin(fs=48khz) mlrck1 (fs=8khz) mbick1 (64fs) adc 1 data bus divide fs=48khz f s= 8khz fs mode [4:0] bits= 0 1 0 1 0 f s= 8khz internal dividing clock mlrck2(fs=48khz) mbick2(64fs) fsmode[4:0] bits= 01010 fs=48khz pll_mclk=122.88mhz mcki pin =3.072mhz sdout1 5 adc2,m sdout1 5 adc1
[ak 4601 ] 016000391 - e - 0 1 - 43 - 201 6 / 12 2 - 4. clko p in output clock the clko pin of the AK4601 outputs a di vided clock of pll mclk. the output frequency setting of the clko pin is controlled by clkosel[2:0] bits ( table 13 ). clkosel[2:0] bits output frequency (fs=48khz base) output frequency (fs=44.1khz base) 000 12.288mhz 11.2896mhz (default) 001 24.576mhz 22.5792 mhz 010 8.192mhz 7.5264mhz 011 6.144mhz 5.6448mhz 100 4.096mhz 3.7632mhz 101 2.048mhz 1.8816mhz table 13 . clko p in setting 2 - 5. bick2/sdin3 pin and lrck2/sdout3 pin settings pin functions of the bick2/sdin3 pin and the lrck2/sdout3 pin are selected by mseln bit. when mseln bit is 0 , the bick2/sdin3 pin works as the bick 2 pin and the lrck2/sdout3 pin works as the lrck2 pin. when mseln bit is 1 , the bick2/sdin3 pin works as the sdin3 pin and the lrck2/sdout3 pin works as the sdout3 pin. m seln bit function 0 bick2 (default) 1 sdin3 table 14 . bick2/sdin3 p in setting 1 2 - 6 . sdinx/ bickx /lrckx p in setting the AK4601 has three sdin pins and two bic k/lrck pins . t hey are independent each other. synchronized channel of the sdinx pin can be select e d by exbckx[2:0] bits from bickx pin and lrckx pin ( table 15 ) . exbckx[2:0] bits bick and lrck pins that synchronizes to sdinx pin 000 tielow (default) 001 bick1 pin , lrck1 pin 010 bick2 pin , lrck2 pin 011 n/a 100 101 110 111 table 15 . bickx /lrckx pin setting for synchronization to sdinx pin msnx bit selects master/slave mode of the bickx pin and the lrckx pin. ( table 16 ) msnx bit bickx pin, lrckx pin 0 slave mode (input) (default) 1 master mode (output) table 16 . bickx pin /lrckx pin mode select
[ak 4601 ] 016000391 - e - 0 1 - 44 - 201 6 / 12 note 43 . set msn x bit to 0 when using the bickx pin as pll reference clock input pin. when m seln bit = 1 , the bick2/sdin3 pin works as sdin3 (input) even setting msn2 bit to 1 , and the lrck2/sdout3 pin works as sdout3 (output) even setting msn2 bit to 0 . m seln bit msn2 bit function 0 0 bick2 (slave mode, input ) lrck2 (slave mode, input ) (default) 0 1 bick2 (master mode, output ) lrck2 (master mode, output ) 1 0 sdin3 (input) sdout3 (output) 1 1 table 17 . bick2/sdin3 p in setting 2 when bickx/lrckx (x=1~ 2 ) pin is set to slave mode, the reference clock of clock sync domain x is the bickx/lrckx pin ( table 7 ). when bickx/lrckx pin is set to master mode, the output clock of the bickx/lrckx pin can be selected from two sync domains by sdbckx[2:0] bits (x= 1~ 2 ) . ( table 18 ) msnx bit sdbckx[2:0] bits bickx pin/lrckx pin 1 000 tielow 1 001 bick sd1, lrck sd1 1 010 bick sd2, lrck sd2 1 011 n/a 1 100 1 101 1 110 1 111 0 xxx input (default) table 18 . clock sync domain setting of bickx/lrckx p in
[ak 4601 ] 016000391 - e - 0 1 - 45 - 201 6 / 12 data path setting 1. data bus, in/output port t he AK4601 has a 32 - bit serial audio stereo data bus ( figure 17 ) . inputs and outputs of each internal block and all input/output pins of the AK4601 are connected to this serial audio data bus. the port that data is input to t his serial audio data bus is defined as input port and the port that data is output from the audio data bus is defined as output port . each port selects clock sync domain and in puts ( outputs ) audio data that synchronized to the reference clock of the clock sync domain to the data bus ( figure 17 ). a stereo data on each port is defined as data source . all data sources are connected to the serial audio bus and a data source on any input port can be output from any output port . data connection of the data bus and a data port with the same sampling frequ ency is define d as data path . input and output port s on the same data path should have the same clock sync domain. if these ports have different clock sync domains, reference clocks (bick sdx, lrck sdx) must be synchronized and the sampling frequency must be the same. phase synchronization of reference clocks is not necessary if the frequency of these clocks are synchronized. however, frequencie s of bick sdx can be different. an src is necessary for data transmission between two ports that have clock sync domain with different sampling frequencies or different reference clock s . figure 17 . data path, input/output port data bus vol1 sdi n1 volo1 sdout1 5 voli1 vol2 sdin1 volo2 sdout1 5 voli2 vol3 sdin1 volo3 sdout1 5 voli3 mixer a sdin1 mixao sdout1 5 mixai2 sdout1 5 mixai1 mixer b sdin1 mixbo sdout1 5 mixbi2 sdout1 5 mixbi1 dac1 sdout1 5 dac 1 sdin1 adc 1 adc1 sdin1 adc 2 adc2 sdin1 adc m adcm sdin1pin sdin2pin sdin3pi n 0 data 0x0000 0000 sdin1 sdout1 5 : input port : output port sdout1pin sdout1 5 sdo ut1 dac2 sdout1 5 dac 2 d ac 3 sdout1 5 dac 3 sdout2pin sdout1 5 sdo ut2 sdout3pin sdout1 5 sdo ut3 sdin1 sdin1 sdin1 sdin2 sdin3 : sync free
[ak 4601 ] 016000391 - e - 0 1 - 46 - 201 6 / 12 1 - 1 . data bus group delay 2*(1/fs) group delay occurs in total as audio data will have group delay of 1*(1/fs) at each input and output port of the data bus that have the same sync domain. therefore, this group delay will increase as the number of times that the data go through the data path increases. 2 . clock sync domain setting for input/output port domain numbers are assigned to each clock sync domain ( table 19 ). each input/output port has setting registers for clock sync domain ( figure 20 ). s et a domain number to cl o ck sync domain setting registers for each input/output port. ( table 20 , table 21 ) domain number clock sync domain 0x 0 reference c l ocks are low (default) 0x 1 sd1 (bick sd1, lrck sd1) 0x 2 sd2 (bick sd2, lrck sd2) table 19 . clock sync domain number if the output port sync domain setting is in auto mode, an audio data port inherits the sync domain of the input data. clock sync domain of the sdinx pin is automatically selected by setting exbckx[2:0] bits, msn bit and sdbckx[2:0] bits ( table 15 , table 16 , table 18 ) . e.g.) sd 2 are selected for clock sync domain of the sdin2 pin when exbck2[2:0] bits = 01 0 and msn 2 bit = 0 ( figure 18 ). figure 18 . clock sync domain setting example1 of sdinx pin e.g.) s d 2 are selected for clock sync domain of the sdin1 pin when exbck 1 [2:0] bits = 0 0 1 , msn 1 bit = 1 and sdbck 1 [2:0] bits = 01 0 ( figure 19 ). figure 19 . clock sync domain setting example2 of sdinx pin
[ak 4601 ] 016000391 - e - 0 1 - 47 - 201 6 / 12 figure 20 . clock sync domain setting of input/output port
[ak 4601 ] 016000391 - e - 0 1 - 48 - 201 6 / 12 2 . source address, source select ing registers a source address is assigned to each input port source ( table 20 ) . t he output port source can be selected by setting a so urce address of input port to the registers. data on the data bus c an be selected freely by this so urce address . in tdm mode, ar bitrar y 2 channels audio data can be output from two selected sdoutx pins ( table 21 ) . source address source name source contents input port clock sync domain setting register ( table 19 ) 0x00 all0 0x0000 0000 fixed all0 - 0x01 sdin1a sdin 1 slot1, 2 input sdin1 note 44 0x02 sdin1b sdin 1 slot3, 4 input 0x03 sdin1c sdin 1 slot5, 6 input 0x04 sdin1d sdin 1 slot7, 8 input 0x05 sdin1e sdin 1 slot9, 10 input 0x06 sdin1f sdin 1 slot11, 12 input 0x07 sdin1g sdin 1 slot13, 14 input 0x08 sdin1h sdin 1 slot15, 16 input 0x09 sdin2 sdin 2 input sdin 2 note 44 0x 0a sdin3 sdin 3 input sdin3 note 44 0x 10 volo1 vol1 output volo1 sdvol1[2:0] 0x 11 volo2 vol2 output volo2 sdvol2[2:0] 0x 12 volo3 vol3 output volo3 sdvol3[2:0] 0x 15 adc1 adc1 output adc1 sdadc1[2:0] 0x 16 adc2 adc2 output codec sdcodec[2:0] 0x 17 adc m adcm output 0x 18 mixer a mixer a output mixer a sdmixa[2:0] 0x 19 mixer b mixer b output mixer b sdmixb[2:0] others n/a n/a n/a n/a (n/a: not available) table 20 . clock sync domain setting for source address and input port note 44 . clock sync domain of the sdinx pin is automatically selected by setting exbckx[2:0] bits, msnx bit and sdbckx[2:0] bits ( table 15 , table 16 , table 18 ) .
[ak 4601 ] 016000391 - e - 0 1 - 49 - 201 6 / 12 set a source address of input data by independent setting registers for each block if each block is obta ining data from the data bus. if the output port sync domain setting is in auto mode, this register setting for source address is not necessary since an audio data port inherits the sync domain of the input data. source select registers contents output port clock sync domain setting register ( table 19 ) seldo1a[5:0] sdout 1 slot1, slot2 sdout1 sddo1[2:0] seldo1b[5:0] sdout 1 slot3, slot4 seldo1c[5:0] sdout 1 slot5, slot6 seldo1d[5:0] sdout 1 slot7, slot8 seldo1e[5:0] sdout 1 slot9, slot10 seldo1f[5:0] sdout 1 slot11, slot12 seldo1g[5:0] sdout 1 slot13, slot14 seldo1h[5:0] sdout 1 slot15, slot16 seldo 2 [5:0] sdout 2 slot1, slot2 sdout2 sddo2[2:0] seldo 3 [5:0] sdout 3 slot1, slot2 sdout3 sddo3[2:0] selda1[5:0] dac1 input dac1 s dcodec[2:0] selda2[5:0] dac2 input dac2 selda3[5:0] dac3 input dac3 selvol1[5:0] vol1 input voli1 (auto) selvol2[5:0] vol2 input voli2 selvol3[5:0] vol3 input voli3 selmixai1[5:0] mixera input1 mixerai1 (auto) selmixai2[5:0] mixera input2 mixerai2 selmixbi1[5:0] mixerb input1 mixerbi1 selmixbi2[5:0] mixerb input2 mixerbi1 table 21 . clock sync domain settings for source select registers and output port
[ak 4601 ] 016000391 - e - 0 1 - 50 - 201 6 / 12 3 . input/output serial interface format 3 - 1 . data clock s the AK4601 h as two in dependent bick/lrck pins that are able to switch master and slave mode . msnx bit selects master/slave mode of the bickx pin and the lrckx pin ( table 16 ). clock format of lrckx/bickx pins can be select ed by dcf x[2:0] bits . if a bick/ lrck pin s are master mode , desirable clock format is ou t put according to dcfx[2:0] bits setting ( table 22 ) . if a bick/lrck pins are slave mode, set dcfx[2:0] bits according to the input clock format . mode dcfx[2] dcfx[1] dcfx[0] clock format 0 0 0 0 i 2 s mode (default) 1 1 0 1 dsp mode 2 1 1 0 pcm short frame 3 1 1 1 pcm long frame table 22 . AK4601 data cl ock format clock edge relation ship can be controlled by bckpx bit. bckpx bit bickx e dge r eferenced to lrckx s tart e dge 0 falling edeg (fe) (default) 1 rising edge (re) table 23 . clock edge relationship between bick x and lrck x
[ak 4601 ] 016000391 - e - 0 1 - 51 - 201 6 / 12 figure 21 . i 2 s mode figure 22 . dsp mode figure 23 . pcm short frame / pcm long frame (bck p x bit = 0 ) figure 24 . pcm short frame / pcm long frame (bckpx bit = 1 ) l ch r ch lrckx bickx l ch r ch lrckx bickx l ch + r ch lrckx bickx l ch + r ch lrckx bickx
[ak 4601 ] 016000391 - e - 0 1 - 52 - 201 6 / 12 3 - 2 . data def inition s a serial bit stream that is sent or received b y the ak4 601 is a digital signal composed of slot, word and bit data . bit: it is a smallest component in a serial data stream. the bit duration is one serial clock cycle. word: it is a group of multiple bits that composes transmitting data between external devices and the AK4601 . figure 25 shows an example of a word consists of eight bits. slot: it is composed of a word and adequate additional bits for interfacing to an external device. in figure 25 , the audio data is an 8 - bit valid data and a 12 - bit slot needs additional four zeros to satisfy an interface protocol of the external device. if the word length is shorter than the slot length, the data alignment of the word will be the beginning of the slot ( msb justified) o r end of the slot ( lsb justified) . figure 25 shows an example of msb justified form at. the slot length must be longer than the word length. figure 25 . bit and word slot definition bit word slot
[ak 4601 ] 016000391 - e - 0 1 - 53 - 201 6 / 12 5 - 3 . input/ output interface format th e AK4601 ha s three digital input ports (sdin1~sdin 3 ) and three digital output ports (sdout1~ sdout 3 ) . the input data format is determined by a combination of dislx[1:0], diedgenx, dilsbex and didlx[1:0] bits settings (x=1~ 3 ). the output data format is determined by a of doslx[1:0], doedgenx, dolsbex and dodlx[1:0] bits settings (x=1~ 3 ). dislx[1:0] bits / doslx[1:0] bits (x=1~ 3 ) control input/output data slot length. dislx[ 1 ] bit d o slx[ 1 ] bit dislx[ 0 ] bit d o slx[ 0 ] bit slot length 0 0 24 bit (default) 0 1 20bit 1 0 16bit 1 1 32bit table 24 . slot length setting of input/output data didlx[1:0] bits / dodlx[1:0] bits (x= 1 ~ 3 ) contro l input/output audio data word length. di dl x[ 1 ] bit dodlx[ 1] bit di dl x[ 0 ] bit dodlx[ 0] bit word length 0 0 24 bit (default) 0 1 20bit 1 0 16bit 1 1 32bit table 25 . word length setting of input/output audio data dilsbex bit / d o lsbex bit (x= 1~ 3 ) selects the audio data format of a slot. dilsbex bit dolsbex bit slot data format 0 msb first (default) 1 lsb first table 26 . slot data format setting diedgenx bi t / d o edgenx bit (x=1~ 3 ) sel ect data transmission start timing of the data after second channel diedgenx bit d o edgenx bit start timing 0 lrck edge basis (default) 1 slot length basis table 27 . data transmission start timing of the data after second channel if the data transmitting timing is set to slot l ength basis, the next channel s data is transmitted immediately without waiting a lrck edge after transmitted one slot data ( figure 29 ~ figure 32 ). if the data transmitting timing is set to lrck edge basis, the next channel s data will not be transmitted until a lrck edge even finished transmitting one slot data ( figure 26 ~ figure 28 ) .
[ak 4601 ] 016000391 - e - 0 1 - 54 - 201 6 / 12 5 - 4 . stereo mode AK4601 supports stereo mode. bick x pin should be set to arbitrary frequency more than word length x 2fs when diedgenx bit = 0 . bick x pin should be set to arbitrary frequency more than slot length x 2fs when diedgenx bit = 1 . b ick clock is supported up to 24.576mhz . the sdinx input pins of the AK4601 suppor t stereo input mode. two slots data input is available for each pin. a source address is assigned to each sdinx input pins when using stereo input mode. ( table 20 ) . disl x [1:0] bits control input data slot length of the sdinx pin. didl x [1:0] bits control the input data word length of the sdinx pin. the slot data format is set by dilsbe x bit . in stereo mode, diedgenx bit must be set to 0 when the data transmission timing of second channel are lrck e dge basis. disl x [1:0] bits setting are ignored when diedgenx bit = 0 . the sdoutx output pins of the AK4601 support stere o output mode. two slots data output is available for each pin. each slot d ata can be assig ned by setting seldoxa - h[5:0] bits . d o sl x [1:0] bits control output data slot length of the sdoutx pin. d o dl x [1:0] bits control the output data word length of the sdoutx pin. the slot data format is set by d o lsbe x bit . in stereo mode, doedgenx bit must be set to 0 when the data transmission timing of second channel are lrck edge basis. d o sl x [1:0] bits setting are ignored when diedgenx bit = 0 . setting example of stereo mode is shown in table 28 . mode data format dcfx[ 2 :0] dilsbex d o lsbex diedgenx d o edgenx dislx[1:0] d o slx[1:0] didlx[1:0] d o dlx[1:0] 0 i 2 s compatible 000 0 0 x word length 1 msb justified 101 0 0 x word length 2 lsb justified 101 1 0 x word length 3 pcm short frame 110 0 1 s lot length word length 4 pcm long frame 111 0 1 s lot length word length 5 irregular i 2 s 000 0 1 s lot length word length table 28 . input/output data format setting example (x: do not c are) 5 - 4 - 1. mode 0 : i2s compatible format figure 26 . i2s compatible format lch data (msb first) s din x lch rch s dout x l rck x b ick x rch data (msb first) dont care dont care lch data (msb first) rch data (msb first)
[ak 4601 ] 016000391 - e - 0 1 - 55 - 201 6 / 12 5 - 4 - 2. mode 1 : msb justified format figure 27 . msb justified format 5 - 4 - 3. mode 2 : lsb justified figure 28 . lsb justified format 5 - 4 - 4. mode 3 : pcm short frame format figure 29 . pcm short frame format (bckpx bit = 0 ) figure 30 . pcm short frame format (bckpx bit = 1 ) lch data (msb first) s din x lch rch s dout x l rck x b ick x rch data (msb first) dont care dont care lch data (msb first) rch data (msb first) lch data (msb first) s din x lch rch s dout x l rck x bick x rch data (msb first) dont care dont care lch data (msb first) rch data (msb first) lch data (msb f irst) s din x s dout x l rck x b ick x rch data (msb first) dont care lch data (msb first) rch data (msb first) tbclk tbclk x bitwidth tbclk x 2 x bitwidth lch da ta (msb first) s din x s dout x l rck x b ick x rch data (msb first) dont care lch data (msb first) rch data (msb first) tbclk tbclk x bitwidth tbclk x 2 x bitwidth
[ak 4601 ] 016000391 - e - 0 1 - 56 - 201 6 / 12 5 - 4 - 5. mode 4 : pcm long frame format figure 31 . pcm long frame format (bckpx bit = 0 ) figure 32 . pcm long frame format (bckpx bit = 1 ) 5 - 4 - 6 . mode 5 : irregular i 2 s format figure 33 . irregular i 2 s format lch data (msb first ) s din x s dout x l rck x (slave) b ick x rch data (msb first) dont care lch data (msb first) rch data (msb first) tbclk tbclk x bitwidth dont care lrck x (master) lch data (msb first) s din x s dout x l rck x (slave) b ick x rch data (msb first) dont care lch data (msb first) rch data (msb first) tbclk tbclk x bitwidth dont care lrck x (master) lch data (msb first) s din x lch rch s dout x l rck x b ick x rch data (msb first) dont care lch data (msb first) rch data (msb first)
[ak 4601 ] 016000391 - e - 0 1 - 57 - 201 6 / 12 5 - 5 . tdm mode AK4601 supports tdm mode. bick clock for data input/output should be set to 128fs, 192fs, 256fs or 512 fs when using tdm mode. up to 192khz in 128fs mode ( max. fs=128khz in 192 mode, max. fs=96khz in 256 mode, max. fs=48k hz in 512 mode ) sampling frequency is supported. the sd in 1 input pin of the AK4601 support tdm mode. sixteen s lots data input is available at a maximum. a source address is assigned to each 2 slot of sd in 1 input pin when using tdm mode. ( table 20 ) . disl 1 [1:0] bits control input data slot length of the sdin 1 pin. didl 1 [1:0] bits control the input data word length of the sdin 1 pin. the slot data format is set by dilsbe 1 bit . in tdm mode, diedgen 1 bit must be s et to 1 since the data transmission timing after second channel are slot length basis. slot length , word length and slot data format of each input data slot should be the same setting. the sdout 1 output pins of th e AK4601 sup port tdm mode. si xteen slots data output is available for each pin at a maximum. each slot d ata can be assig ned independently by setting seldo 1 a - h[5:0] bits in every two slots. d o sl 1 [1:0] bits control output data slot length of the sd out 1 pin. d o dl 1 [1:0] bits control the output data word length of the sdout 1 pin. the slot data format is set by d o lsbe 1 bit . in tdm mode, d o edgen 1 bit must be set to 1 since the data transmission timing after second channel are slot length basis. slot length , word length and slot data format of each input data slot should be the same setting. setting example of tdm mode is shown in table 29 . mode data format dcf 1 [ 2 :0] dilsbe 1 d o lsbe 1 diedgen 1 d o edgen 1 disl 1 [1:0] d o sl 1 [1:0] didl 1 [1:0] d o dl 1 [1:0] 0 i 2 s compatible 000 0 1 11 (32bit) word length 1 msb justified 101 0 1 11 (32bit) word length 2 lsb justified 101 1 1 11 (32bit) word length 3 pcm short frame 110 0 1 s lot length word length 4 pcm long frame 111 0 1 s lot length word length 5 irregular i 2 s 000 0 1 s lot length word length table 29 . tdm mode setting example
[ak 4601 ] 016000391 - e - 0 1 - 58 - 201 6 / 12 5 - 5 - 1. i2s compatible format figure 34 . tdm m ode i 2 s compatibl e ( bick = 512 fs ) figure 35 . tdm m ode i 2 s compatible ( bick = 256fs ) figure 36 . tdm m ode i 2 s compatible ( bick = 128fs ) 512 bick sdin 1 /sdout 1 bick x l rck x 32 bick slot1 6 32 bick slot1 32 bick slot2 32 bick slot 3 32 bick slot 4 32 bick slot 5 32 bick slot6 32 bick slot7 32 bick slot 8 32 bick sl ot 9 32 bick slot1 0 32 bick slot1 1 32 bick slot1 2 32 bick slot1 3 32 bick slot1 4 32 bick slot1 5 256bick sdin 1 /sdout 1 bick x 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick 3 2 bick 32 bick s lot1 s lot 2 s lot 3 s lot 4 s lot 5 s lot 6 s lot 7 s lot 8 l rck x 128 bick sdin 1 /sdout 1 bick x l rck x 32 bick 32 bick 32 bick 32 bick s lot1 s lot2 s lot3 s lot4
[ak 4601 ] 016000391 - e - 0 1 - 59 - 201 6 / 12 5 - 5 - 2. msb justified format figure 37 . tdm m ode msb justified for mat ( bick = 512fs ) figure 38 . tdm m ode msb justified format ( bick = 256fs ) figure 39 . tdm m ode msb justified format ( bick = 128fs ) 512 bick sdin 1 /sdout 1 bick x 32 bick slot1 32 bick slot1 6 32 bick slot2 32 bick slot 3 32 bick slot 4 32 bick s lot 5 32 bick slot6 32 bick slot7 32 bick slot 8 32 bick slot 9 32 bick slot1 0 32 bick slot1 1 32 bick slot1 2 32 bick slot1 3 32 bick slot1 4 32 bick slot1 5 l rckx 256bick sdin 1 / sdout 1 bick x l rck x 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick s lot1 s lot 2 s lot 3 s lot 4 s lot 5 s lot 6 s lot 7 s lot 8 128 bick sdin 1 /sdout 1 bick x l rck x 32 bick 32 bick 32 bick 32 bick s lot1 s lot2 s lot3 s lot4
[ak 4601 ] 016000391 - e - 0 1 - 60 - 201 6 / 12 5 - 5 - 3. lsb justified format figure 40 . tdm m ode lsb justified format ( bick = 512fs ) figure 41 . tdm m ode lsb justified format ( bick = 256fs ) figure 42 . tdm m ode lsb justified format ( bick = 128fs ) sdin 1 /sdout 1 bick x 32 bick slot1 32 bick slot1 6 32 bick slot2 32 bick slot 3 32 bick slot 4 32 bick slot 5 32 bick slot6 32 bick s lot7 32 bick slot 8 32 bick slot 9 32 bick slot1 0 32 bick slot1 1 32 bick slot1 2 32 bick slot1 3 32 bick slot1 4 32 bick slot1 5 512bick l rckx 256bick sdin 1 / sdout 1 bick x l rck x 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick s lot1 s lot 2 s lot 3 s lot 4 s lot 5 s lot 6 s lot 7 s lot 8 128 bick sdin 1 /sdout 1 bick x l rck x 32 bick 32 bick 32 bick 32 bick s lot1 s lot2 s lot3 s lot4
[ak 4601 ] 016000391 - e - 0 1 - 61 - 201 6 / 12 5 - 5 - 4. pcm short frame format figure 43 . tdm mode pcm short frame ( bick = 512fs , bckp bit = 0 ) ( note 45 ) figure 44 . tdm mode pcm short frame ( bick = 256fs , bckp bit = 0 ) ( note 45 ) figure 45 . tdm mode pcm short frame ( bick = 128fs , bckp bit = 0 ) ( note 45 ) note 45 . when bckpx bit = 1 , a bick rising edge corresponds to a lrck rising edge . 512 bick sdin 1 bick x l rck x slot 6 slot 7 slot 8 slot 9 slot1 0 slot 1 1 slot1 2 slot1 3 slot1 4 slot1 5 slot1 6 don t care slot1 slot 2 slot 3 slot 4 slot 5 sdoutx 256bick sdin 1 bick x l rck x s lot 2 s lot 3 s lot 4 s lot 5 s lot 6 s lot 7 s lot 8 sdout 1 don t care s lot1 128 bick sdin 1 bick x l rck x s lot2 s lot3 s lot4 don t care sdout 1 s lot1
[ak 4601 ] 016000391 - e - 0 1 - 62 - 201 6 / 12 5 - 5 - 5. pcm long f rame format figure 46 . tdm mode pcm long frame ( bick = 512fs , bckp bit = 0 ) ( note 46 ) figure 47 . tdm mode pcm long frame ( bick = 256fs , bckp bit = 0 ) ( note 46 ) figure 48 . tdm mode pcm lo ng frame ( bick = 128fs , bckp bit = 0 ) ( note 46 ) note 46 . when bckpx bit = 1 , a bick rising edge corresponds to a lrck rising edge . 512 bick bick x lrck x ( slave ) l rck x (master) slot 6 slot 7 slot 8 slot 9 slot1 0 slot 1 1 slot1 2 slot1 3 slot1 4 slot1 5 slot1 6 slot1 dont care slot 2 slot 3 slot 4 slot 5 sdin 1 don t care sdout 1 256bick bick x lrck x ( slave ) l rck x (master) s lot 2 s lot 3 s lot 4 s lot 5 s lot 6 s lot 7 s lot 8 s lot1 don t care sdin 1 sdout 1 don t care 128 bick bick x lrck x ( slave ) l rck x (master) s lot1 s lot2 s lot3 s lot4 dont care sdin 1 don t care sdout 1
[ak 4601 ] 016000391 - e - 0 1 - 63 - 201 6 / 12 5 - 5 - 6. ir regular i 2 s format figure 49 . tdm mode ir regular i 2 s for mat ( bick = 512fs ) figure 50 . tdm mode irregular i 2 s format ( bick = 256fs ) figure 51 . tdm mode irregular i 2 s format ( bick = 128fs ) 512 bick bick x lrck x ( slave ) l rck x (master) slot 6 slot 7 slot 8 slot 9 slot1 0 slot 1 1 slot1 2 slot1 3 slot1 4 slot1 5 slot1 6 dont care slot 2 slot 3 slot 4 slot 5 sdin 1 don t care sdout 1 slot 1 256bick bick x s lot 2 s lot 3 s lot 4 s lot 5 s lot 6 s lot 7 s lot 8 lrck x (slave) dont care sdin 1 sdout 1 don t care s lot1 l rck x (master) 128 bick bick x s lot2 s lot3 s lot4 lrck x ( slave ) dont care sdin 1 don t care sdout 1 s lot1 l rck x (master)
[ak 4601 ] 016000391 - e - 0 1 - 64 - 201 6 / 12 power - up sequence . power - up sequence the AK4601 should be powered up when the pdn pin = l. set the pdn pin to h to start the power supply circuits for ref (reference voltage source) generator and digital circuits after all power supplies are fed. by setting the pdn pin to h , control registers are initialized. control register settings should be made with an interval of 1ms or more after the pdn pin = h. the pll starts operation by a clock reset release ( ckresetn bit = 0 1) and generates the internal master clock aft er setting control registers. therefore, necessary system clock must be input before a clock reset release. the system clock must not be stopped except during clock reset and power - down mode (pdn pin = l ) . figure 52 . power - up sequence note 47 . the analog input charge period depends on the capacitance of ac coupling capacitor. it will be 100 msec if the capacitance is 1 f. note 48 . the output period of a stable microphone power depends on the capacitance of decoupling capacitor at the mpref pin. it will be 100 msec if the capacitance is 1 f. power supply pdn pin analog input si / sda pin pmmb1 bit pmmb2 bit mic power output ckresetn bit hresetn bit mcki, bickx pin pll internal master clock analog input charge cont cont reg setting reg setting stable mic power output 600ns (min) 100 ms 1ms (min) 10 ms 100 ms clock determined period until pll oscillation start operation
[ak 4601 ] 016000391 - e - 0 1 - 65 - 201 6 / 12 ldo (internal circuit drive regulator) the AK4601 has a regulator for driving internal digital circuits (ldo). connect a 2.2 f (30%) capacitor between the avdrv pin and the d vs s 2 p in. the ldo starts operation by releasing power - down mode, and control register settings can be made 1ms after the power - dow n release (pdn pin= h ) . the AK4601 has an overcurrent protection circuit to avoid abnormal heat of the device that is caused by a short of the avdrv pin to vss and etc., and an overvoltage protection circuit to protect from exceeded voltage when the volt age to the avdrv pin gets too high. when these protection circuits perform, internal circuits are powered down. the internal circuit will not return to a normal operation until being reset by the pdn pin after removing the problems. power - down and reset 1 . AK4601 power - down and reset s tatuses and power manageme nt power - down and power - down release of the AK4601 is controlled by the pdn pin. after power - down is released, the power management and reset of the AK4601 are controlled by registers such as ckresetn bit (clock reset) and power management bits for each block. there are two states for the AK4601 other than normal operation: power - down and clock reset. the power - down state means the status that the pdn pin i s l . in this state, all blocks of the AK4601 stop the operation. the clock reset state means the status that the pdn pin is h and ckresetn bit is 0 . in this state, the adc, dac , blocks are not in operation because the pll circuit and internal clocks are stopped. state setting pdn pin ckresetn bit power - down l x clock reset h 0 clock reset release h 1 ( note 49 ) table 30 . reset state definitions of t h e AK4601 (x: do nt care) note 49 . a stable clock should be supplied before releasing clock reset (ckresetn bit = 1 ). 2. power - down th e AK4601 c an be powered down by bringing the pdn pin = l. output statuses of power - down mode are shown in table 3 . 3. power - down release the ref generation circuit (reference voltage source) and a power supply circuit for internal digital circuit are powered - up by bringing the pdn pin to h from l after an interval of 600ns or more when a vdd , lvdd , tvdd are powered up. control register settings should be made with an interval of 1ms or longer after setting the pdn pin = h .
[ak 4601 ] 016000391 - e - 0 1 - 66 - 201 6 / 12 4. clock reset when ckresetn bit = 0 after power - down mode is released (pdn pin = h), the AK4601 is in clock reset state. all blocks except the power supply circuits for ref generation and digital circuits are in power - save mode. even the internal pll for master clock generation is powered down. control register settings should be made with an interval of 1ms (min) or more after releasing the power - down mode. necessary system clock s ( table 4 , table 5 ) should be i nput before the clock reset is released. th e internal pll starts operation and the master clock is generated when clock reset is released (ckresetn bit = 1) ( figure 52 ) . th e AK4601 will be in operation by releasing power - down mode of the block s by setting each power - management bit . system clocks must be changed during clock reset or in power - down mode (pdn pin = l). the pll and the internal clock s are stopped by this clock reset and the clock change can be done safely. change register settings and system clock frequencies during the clock reset. after s ystem c l ock is stabilized, the pll starts operation by setting ckresetn bit to 1. clock operated blocks (adc and dac) must be powered down before executing clock reset. these blocks can be powered down simultaneously by setting hresetn bit to 0 from 1 (each pmad and pmda bits settings are not necessary). set hresetn bit to 1 from 0 with an interval of 10ms for stabilization of pll after clock reset is released. figure 53 . clock mode switching sequence cs n sclk (simplified) si mcki b ick 1 pllref mode 0 pllref mode 1 h reset n bit ckr e s e t n bit pll stop input clock and clock mode can be changed pll stabilize blocks except pll are stopped c0 00 84 00 c0 00 01 00 00 00 29 87 c0 c0 00 84 0f resume operation
[ak 4601 ] 016000391 - e - 0 1 - 67 - 201 6 / 12 sto b it status pll lock signal can be read out from th e sto bit when plllocke bit = 1 . plllocke bit sto bit note 0 no error detected: 1 (default) 1 no error detected: 1 plllock error detected: 0 table 31 . sto b it status p interface setting and pin status th e AK4601 supports both spi and i 2 c interfaces. when using spi interface, release the power - down state of the AK4601 while the csn pin is h . after a power - down release, the AK4601 is set to i 2 c interface mode. spi interface mode become enabled by sending the dummy command mentioned below. input 0xde 0xadda 0x7a to the si/i2cfil pin while the csn pin is l for the dummy command. the data is in msb first format. figure 54 . dummy command write sequence statuses of the so/sda , sclk/scl and si/i2cfil pin s are changed depending on the csn and pdn pins. csn pin pdn pin so/sda pin sclk/scl pin si/i2cfil pin spi interface l l hi - z input input l h function function function i 2 c interface h l hi z pull 2 c fast mode) h ( i 2 c fast mode plus) table 32 . p interface setting note 50 . the csn pin and the si/i2cfil pin should be fixed to l or h when using i 2 c interface mode. cs n sclk si 0x de (8bit) 0x adda (16bit ) 0x 7a ( 8bit ) dont care (l/h) dont care (l/h)
[ak 4601 ] 016000391 - e - 0 1 - 68 - 201 6 / 12 spi interface 1 . register write (1) control register write field write data (1) command code 0x c 0 (2) address a15 ~ a8 ( 3 ) address a 7~ a 0 ( 4 ) data d7~d0 one byte of data may be written continuously for each address. 2 . register read (1) control register read field write data readout data (1) command code 0x40 (2) address a15 ~ a8 ( 3 ) address a 7~ a 0 ( 4 ) data d7~d0 one byte of data may be read continuously for each address. write operation figure 55 . spi interface timing ( write ) read operation figure 56 . spi interface timing (read) cs n sclk si command code (8bit) address (16bit ) data (write) so dont care (l/h) hi - z hi - z dont care (l/h) l ow cs n sclk si command code (8bit) address (16bit ) data ( read ) so dont care (l/h) hi - z hi - z dont care (l/h) low
[ak 4601 ] 016000391 - e - 0 1 - 69 - 201 6 / 12 i 2 c bus interface ( csn = h) access to th e AK4601 registers and ram can be controlled by an i2c bus. the AK4601 sup ports fast - mode i 2 c - bus (max: 400khz) and fast - mode plus (max: 1mhz) . si/i2cfil pin bus mode l fast mode h fast mode plus table 33 . i 2 c bus mode setting note 51 . the AK4601 does not support hs mode (max: 3.4mhz) . 1. data transfer in order to access any ic devices on the i 2 c bus, input a start condition first, followed by one byte of slave address which includes the device address. ic devices on the bus compare this device address with their own address es and the ic device which has an identical address with the device address generates an acknowledgement. an ic device with the identical address then executes either a read or a write operation. after the command execution, input a stop condition. 1 - 1. dat a change change the data on the sda line while the scl line is l. the sda line condition must be stable and fixed while the clock is h. change the data line condition between h and l only when the clock signal on the scl line is l. change the sd a line condition while the scl line is h only when the start condition or stop condition is input. figure 57 . data change ( i 2 c ) 1 - 2. start condition and stop condition a start condition is generated by the transition of h to l on the sda line while the scl line is h. all instructions are initiated by a start condition. a stop condition is generated by the transition of l to h on the sda line while the scl line is h. all instructions end by a stop condition. figu re 58 . start condition and stop condition ( i 2 c ) scl sda data line stable : data valid change of data allowed scl sda stop condition start condition
[ak 4601 ] 016000391 - e - 0 1 - 70 - 201 6 / 12 1 - 3. repeated start condition when a start condition is received again instead of a stop condition, the bus changes to a repeated start condition. a repeated start condition is functionally the same as a start condition. figure 59 . repeated start condition ( i 2 c ) 1 - 4. acknowledge the ic device that sends data releases the sda line (h) after sending one byte of data. the ic device that receives data then sets the sda line to l at the next clock. this operation is called acknowledgement, and it enables verification that the data transfer has been properly executed. the AK4601 generates an acknowledgement upon receipt of a start condition and a sla ve address. for a write instruction, an acknowledgement is generated whenever receipt of each byte is completed. for a read instruction, succeeded by generation of an acknowledgement, the AK4601 releases the sda line after outputting data at the designated address, and it monitors the sda line condition. when the master side generates an acknowledgement without sending a stop condition, the AK4601 outputs data at the next address location. when no acknowledgement is generated, the AK4601 ends data output (n ot acknowledged). figure 60 . generation of acknowledgement scl sda repeated start condition start condition scl fro m master acknowledge data output by transmitter data output by receiver 1 9 8 start condition clock pulse for acknowledge not acknowledge
[ak 4601 ] 016000391 - e - 0 1 - 71 - 201 6 / 12 1 - 5. the first byte the first byte, which includes the slave - address, is input after the start condition is set, and a target ic device that will be accessed on the bus is selected by the slave - address. the slave - address is configured with the upper 7 - bits and the data is 0010000 . when the slave - address is inputted, an external device that has the identical device address generates an acknowledgement and instru ctions are then executed. the 8 th bit of the first byte (lowest bit) is allocated as the r/w bit. when the r/w bit is 1, the read instruction is executed, and when it is 0, the write instruction is executed. note 52 . in this doc ument, there is a case that describes a write slave - address assignment when both address bits match and a slave - address at r/w bit = 0 is received. there is a case that describes read slave - address assignment when both address bit s matches and a slav e - address at r/w bit = 1 is received. 0 0 1 0 0 0 0 r/w figure 61 . first byte configuration ( i 2 c ) 1 - 6. the second and succeeding bytes the data format of the second and succeeding bytes of t he AK4601 transfer / receive serial data (command code, address and data in microcontroller interface format) on the i 2 c bus are all configured with a multiple of 8 - bits. when transferring or receiving those data on the i 2 c bus, they are divided into an 8 - bit data stream segment and they are transferred / received with the msb side data first with an acknowledgement in - between. example ) when transferring / receiving a1b2c3 (hex) 24 - bit serial data in microprocessor interface format: figure 62 . division of data ( i 2 c ) note 53 . in this document, there is a case that describes a write instruction command code which is received at the second byte as write command. there is a case that describes a read instruction command code which is received at the second byte as read command. a1 b2 c3 a1 b2 c3 a a 24bit 8bit 8bit 8bit a acknowledge (1) microcomputer format (1) i 2 c format
[ak 4601 ] 016000391 - e - 0 1 - 72 - 201 6 / 12 2. write sequence in th e AK4601 , wh en a write - s lave - address assignment is received at the first byte, the write command at the second byte, the address at the third and fourth bytes, and data at the fifth and succeeding bytes are received. the number of write data bytes is fixed by the received command code. figure 63 . write sequence ( i 2 c ) 3. read sequence in th e AK4601 , when a write - slave - address assignment is received at the first byte, the read command at the second byte and the address at the third and fourth bytes are received. when the fourth byte is received and an acknowledgement is transferred, the read command waits for the next restart condition. when a read slave - address assignment is received at the first byte, data is transferred at the second and succeeding bytes. the number of readable data bytes is fixed by the received read command. after reading the last byte, assure that a not acknowledged signal is received. if this not acknowledged signal is not received, the AK4601 conti nues to send data regardless whether data is present or not, and since it did not release the bus, the stop condition cannot be properly received. figure 64 . read sequence ( i 2 c ) 4 . limitation in use of i 2 c interface the i 2 c interface does not support the following features. (1) no operation in hs mode (max: 3.4mhz). th e AK4601 supports f ast mode (max: 400 k hz) and fast plus mode (max: 1mhz) . note 54 . do not turn off the power of the AK4601 whenever the power supplies of other devices of the same system are turned on. pull - up resistors of sda and scl pins should be connected to tvdd or less voltage. (the diode s against tvdd exist in the sda and scl pins.) sda command code s slave address address(0) address(1) data( 0 ) data( 1 ) data( n ) p r/w= 0 t r s a t a c k a c k a c k a c k a c k a c k a c k a c k s t o p sda command code address(0) address(1) p r/w= 0 t r s a t a c k a c k a c k a c k s t o p s slave address r/w= 1 e a s t r t r da ta( 0 ) data( 1 ) a c k a c k s slave address data( n ) a c k a c k m t a s e r m t a s e r m t a s e r m t a s e r n a c k
[ak 4601 ] 016000391 - e - 0 1 - 73 - 201 6 / 12 m ixer th e AK4601 has two stere o input mixers that have level adjustment function for overflow protection after adding and data change function (mixer a and mixer b). level adjustment is processed by shift operation. since the level adjustment function is only for avoiding ove rflow by adding, it can only shift 1bit to the right. mixer a is controlled by sfta1[1:0] bits, s fta2[1:0] bits, swpa1[1:0] bits and swpa2[1:0] bits . mixer b is controlled by sftb1[1:0] bits, s ftb2[1:0] bits, swpb1[1:0] bits and swpb2[1:0] bits . figure 65 . block diagram of the mixer mode sfta1[1:0] / sfta2[1:0] bits sftb1[1:0] / sftb2[1:0] bits shift amount l(y) (y=1 or 2) r(y) (y=1 or 2) comment 0 00 no shift l(y) r(y) 0db 1 01 1 bit right shift l(y) >> 1 r(y) >>1 about - 6db (x 1/2) 2 10 mute 0 0 - db 3 11 table 34 . level adjustment of the mixer mode swpa1[1:0] / swpa2[1:0] bits swpb1[1:0] / swpb2[1:0] bits l(y) r(y) comment 0 00 l(y) r(y) l(y) l(y) lin lout, rout r(y) r(y) rin lout, rout r(y) l(y) lin rout rin lout table 35 . data change function of the mixer stereo ( 1) l( 1 ) r ( 1 ) l( 1 ) r ( 1 ) l( 1 ) r ( 1 ) shift or mute stereo ( 2 ) l( 2 ) r ( 2 ) l( 2 ) r ( 2 ) l( 2 ) r ( 2 ) l( q ) r ( q ) stereo ( q ) serial data bus swp x 1 [1:0] sftx 1 [1:0] swp x2[1:0] x = a or b serial data bus shift or mute selmix x i 1 [ 5:0] selmix x i 2 [ 5 :0] sftx2[1:0]
[ak 4601 ] 016000391 - e - 0 1 - 74 - 201 6 / 12 vol the AK4601 has three digital volume circuits (+12~ - 115db, 0.5db steps) that have independent lch and rch. vol1 lch vol 1 l[7:0] vol1 r ch vol 1r [7:0] vol2 lch vol 2 l[7:0] vol2 rch vol 2 r[7:0] vol3 lch vol 3 l[7:0] vol3 rch vol 3 r[7:0] attenuation level 00h 00h 00h 00h 00h 00h +12.0db 01h 01h 01h 01h 01h 01h +11.5db 02h 02h 02h 02h 02h 02h +11.0db : : : : : : : 17h 17h 17h 17h 17h 17h +0.5db 18h 18h 18h 18h 18h 18h 0.0db (default) 19h 19h 19h 19h 19h 19h - 0.5db : : : : : : : fdh fdh fdh fdh fdh fdh - 114.5db feh feh feh feh feh feh - 115.0db ffh ffh ffh ffh ffh ffh mute ( - ) atspvol bit controls transition time between setting values of the volume. mode atsp vol att speed 0 0 4 /fs (default) 1 1 16 /fs table 37 . volume transition time when changing output levels, transitions are executed via soft changes; thus no switching noise occurs during these transit ions. in mode 0, i t takes 102 0 /fs ( 21 .3ms@fs=48khz) from 18 h(0db) to ffh(mute). if t he pdn pin goes to l, each channel of volume circuit is initialized to 18 h. atsp vol 00h ?
[ak 4601 ] 016000391 - e - 0 1 - 75 - 201 6 / 12 table 39 . digital volume level setting of the vol circuit code db code db code db code db code db code db code db code db 00h 12.0 20h - 4.0 40h - 20.0 60h - 36.0 80h - 52.0 a0h - 68.0 c0h - 84.0 e0h - 100.0 01h 11. 5 21h - 4.5 41h - 20.5 61h - 36.5 81h - 52.5 a1h - 68.5 c1h - 84.5 e1h - 100.5 02h 11.0 22h - 5.0 42h - 21.0 62h - 37.0 82h - 53.0 a2h - 69.0 c2h - 85.0 e2h - 101.0 03h 10.5 23h - 5.5 43h - 21.5 63h - 37.5 83h - 53.5 a3h - 69.5 c3h - 85.5 e3h - 101.5 04h 10.0 24h - .6.0 44h - 22.0 64h - 38.0 84h - 54.0 a4h - 70.0 c4h - 86.0 e4h - 102.0 05h 9.5 25h - 6.5 45h - 22.5 65h - 38.5 85h - 54.5 a5h - 70.5 c5h - 86.5 e5h - 102.5 06h 9.0 26h - 7.0 46h - 23.0 66h - 39.0 86h - 55.0 a6h - 71.0 c6h - 87.0 e6h - 103.0 07h 8.5 27h - 7.5 47h - 23.5 67h - 39.5 87h - 55.5 a7h - 71.5 c7h - 87.5 e7h - 103.5 08h 8.0 28h - 8.0 48h - 24.0 68h - 40.0 88h - 56.0 a8h - 72.0 c8h - 88.0 e8h - 104.0 09h 7.5 29h - 8.5 49h - 24.5 69h - 40.5 89h - 56.5 a9h - 72.5 c9h - 88.5 e9h - 104.5 0ah 7.0 2ah - 9.0 4ah - 25.0 6ah - 41.0 8ah - 57.0 aah - 73.0 cah - 89.0 eah - 105.0 0bh 6.5 2bh - 9.5 4bh - 25.5 6bh - 41.5 8bh - 57.5 abh - 73.5 cbh - 89.5 ebh - 105.5 0ch 6.0 2ch - 10.0 4ch - 26.0 6ch - 42.0 8ch - 58.0 ach - 74.0 cch - 90.0 ech - 106.0 0dh 5.5 2dh - 10.5 4dh - 26.5 6dh - 42.5 8dh - 58.5 adh - 74.5 cdh - 90.5 edh - 106.5 0eh 5.0 2eh - 11.0 4eh - 27.0 6eh - 43.0 8eh - 59.0 aeh - 75.0 ceh - 91.0 eeh - 107.0 0fh 4.5 2fh - 11.5 4fh - 27.5 6fh - 43.5 8fh - 59.5 afh - 75.5 cfh - 91.5 efh - 107.5 10h 4.0 30h - 12.0 50h - 28.0 70h - 44.0 90h - 60.0 b0h - 76.0 d0h - 92.0 f0h - 108.0 11h 3.5 31h - 12.5 51h - 28.5 71h - 44.5 91h - 60.5 b1h - 76.5 d1h - 92.5 f1h - 108.5 12h 3.0 32h - 13.0 52h - 29.0 72h - 45.0 92h - 61.0 b2h - 77.0 d2h - 93.0 f2h - 109.0 13h 2.5 33h - 13.5 53h - 29.5 73h - 45.5 93h - 61.5 b3h - 77.5 d3h - 93.5 f3h - 109.5 14h 2.0 34h - 14.0 54h - 30.0 74h - 46.0 94h - 62.0 b4h - 78.0 d4h - 94.0 f4h - 110.0 15h 1.5 35h - 14.5 55h - 30.5 75h - 46.5 95h - 62.5 b5h - 78.5 d5h - 94.5 f5h - 110.5 16h 1.0 36h - 15.0 56h - 31.0 76h - 47.0 96h - 63.0 b6h - 79.0 d6h - 95.0 f6h - 111.0 17h 0.5 37h - 15.5 57h - 31.5 77h - 47.5 97h - 63.5 b7h - 79.5 d7h - 95.5 f7h - 111.5 18h 0.0 38h - 16.0 58h - 32.0 78h - 48.0 98h - 64.0 b8h - 80.0 d8h - 96.0 f8h - 112.0 19h - 0.5 39h - 16.5 59h - 32.5 79h - 48.5 99h - 64.5 b9h - 80.5 d9h - 96.5 f9h - 112.5 1ah - 1.0 3ah - 17.0 5ah - 33.0 7ah - 49.0 9ah - 65.0 bah - 81.0 dah - 97.0 fah - 113.0 1bh - 1.5 3bh - 17.5 5bh - 33.5 7bh - 49.5 9bh - 65.5 bbh - 81.5 dbh - 97.5 fbh - 113.5 1ch - 2.0 3ch - 18.0 5ch - 34.0 7ch - 50.0 9ch - 66.0 bch - 82.0 dch - 98.0 fch - 114.0 1dh - 2.5 3dh - 18.5 5dh - 34.5 7dh - 50.5 9dh - 66.5 bdh - 82.5 ddh - 98.5 fdh - 114.5 1eh - 3.0 3eh - 19.0 5eh - 35.0 7eh - 51.0 9eh - 67.0 beh - 83.0 deh - 99.0 feh - 115.0 1fh - 3.5 3fh - 19.5 5fh - 35.5 7fh - 51.5 9fh - 67.5 bfh - 83.5 dfh - 99.5 ffh mute
[ak 4601 ] 016000391 - e - 0 1 - 76 - 201 6 / 12 analog input blcok 1. microphone input gain th e AK4601 ha s gain amplifiers for microphone input. the gain of l and r channels can be independently selected by mgnl[3:0] and mgnr[3:0] bits ( table 40 ) . the input impedance is typ. 20k ? @ adc1vl/r bit = 0 and typ. 25k ? @ adc1vl/r bit = 1 . this gain amplifier executes zero crossing detection when changing the gain by setting micl zce bit = 1 / micrzce bit = 1 . zero crossing detection is executed independently for l and r channels. zero crossing timeout period is 16ms@fs=48khz. when miclzce bit = 0 / micrzce bit = 0 , the volume is changed immediately by register settings. when writing to mgnl/r[3:0] bits continu ously , take an interval of zero cross ing timeout period or more. if the mgnl/r[3:0] bits are changed before zero crossing, the volume of lch and rch may differ. when the volume level that is same as the present volume is set, the zero crossing counter is not reset and time out s according to the previous writing timing. therefore , in this case, writing to mgnl/r [3:0] bits continuously is possible with a shorter interval of the zero crossing timeout period. 1 - 1. microphone input selector mode mgnl[3] mgnr[3] mgnl[2] mgnr[2] mgnl[1] mgnr[1] mgnl[0] mgnr[0] input gain 0 0 0 0 0 0db (default) 1 0 0 0 1 2db 2 0 0 1 0 4db 3 0 0 1 1 6db 4 0 1 0 0 8db 5 0 1 0 1 10db 6 0 1 1 0 12db 7 0 1 1 1 14db 8 1 0 0 0 16db 9 1 0 0 1 18db a 1 0 1 0 21db b 1 0 1 1 24db c 1 1 0 0 27db d 1 1 0 1 30db e 1 1 1 0 33db f 1 1 1 1 36db table 40 . microphone input gain 1 - 2 . zero crossing timeout the microphone gain is changed independently on the timing of zero crossing detection or zero crossing timeout. pll_mclk zero crossing timeout period 48khz base 122.880mhz 16.0ms 44.1khz base 112.986mhz 17.4ms table 41 . zero crossing timeout period 1 - 3 . start - up time of mic input pin the AK4601 sta rts to charge a dc cut capacitor when the pdn pin is set to h from l . since the input impedanc e is 25 k , t he time constant will be 2 5 ms if the dc cut capacitor is 1 f. a wait time of about 100ms should be taken before power up the adc to charge the dc cut capacitor sufficiently. a click noise may occur just after the adc is powered up if this wait time is n ot enough .
[ak 4601 ] 016000391 - e - 0 1 - 77 - 201 6 / 12 2. microphone input selector t h e AK4601 has micr ophone input selectors. each microphone amplifier input is selectable between single - ended input and differential input by ad1lsel bi t or ad1rsel bit . figure 66 . microphone input selector ad1lsel bit adc lch ad1rsel bit adc rch 0 inp1/inn 1 (d efault ) 0 inp2/inn2 (d efault ) 1 ain 1 l 1 ain 1 r table 42 . microphone input selector 3. microphone bias output the AK4601 has t wo lin es of microphone bias outputs. the power supply of microphones are supplied from the mpwr1 pin and the mpwr2 pin by setting pmmb1 bit = 1 and pmmb2 bit = 1 , respectively. the output voltage is 2.5v (avdd=3.3v) and the load resistance is min. 2k . pmmb 1 bit mpwr1 pin pmmb 2 bit mpwr2 pin 0 hi - z (d efault ) 0 hi - z (d efault ) 1 output 1 output table 43 . microphone bias output figure 67 . mic block circuit (differential input) figure 68 . mic block circuit (single - end input) ain 1 l / inp1 pin ak 460 1 mic - amp rch inn1 pin adc lch ad1lsel bit mic - amp lch adc rch ain 1 r / inp2 pin inn2 pin ad1rsel bit inp1 ak 460 1 microphone 0. 1 f 2k mpwr1 pin pmb 1 bit mpwr2 pin pmb2 bit mic - amp lch inn1 microphone 2k 2k 2k inp2 inn2 mic - amp rch 0. 1 f ain 1 l ak 460 1 microphone 0. 1 f mpwr1 pin pmb 1 bit mpwr2 pin pmb2 bit mic - amp lch microphone 2k 2k ain 1 r mic - amp rch 0. 1 f
[ak 4601 ] 016000391 - e - 0 1 - 78 - 201 6 / 12 adc block ( adc1 , adc2 , adc m ) 1. adc block high pass filter the AK4601 has a digital high pass filter (hpf) for dc offset cancelling of each adc. the cut - off fre quency of the hpf is about 0.93hz (fs=48khz) , depending on operation frequency. fs 48khz 44.1khz 8khz cut - off frequency 0.93 hz 0.86 hz 0. 16 hz table 44 . hpf cut - off frequency 2 . adc digital volume the AK4601 has in dependent digital volume controls for lch and rch (256 levels, 0.5db steps) of each adc. adc 1 volad 1 l[7:0] adc 1 volad 1 r [7:0] adc 2 volad 2l [7:0] adc 2 volad 2r [7:0] adc m vol ad m [7:0] attenuation level 00h 00h 00h 00h 00h +24.0db 01h 01h 01h 01h 01h +23.5db 02h 02h 02h 02h 02h +23.0db : : : : : : 2fh 2fh 2fh 2fh 2fh +0.5db 30h 30h 30h 30h 30h 0.0db (default) 31h 31h 31h 31h 31h - 0.5db : : : : : : fdh fdh fdh fdh fdh - 102.5db feh feh feh feh feh - 103.0db ffh ffh ffh ffh ffh mute ( - ) the transition time between set values is selected by atspad bit . mode atspad bit att speed 0 0 4/fs (default) 1 1 16/fs table 46 . adc volume level transition time when changing output levels, transitions are executed via soft changes; thus no switching noise occurs during these transitions. in mode 0, i t takes 102 0 /fs ( 21 .3ms@fs=48khz) from 00h(0db) to ffh(mute). if the pdn pin goes to l, each channel of the adc is initialized to 3 0h. atspad bit 00h ?
[ak 4601 ] 016000391 - e - 0 1 - 7 9 - 201 6 / 12 code db code db code db code db code db code db code db code db 00h 24.0 20h 8.0 40h - 8.0 60h - 24.0 80h - 40.0 a0h - 56.0 c0h - 72.0 e0h - 88.0 01h 23.5 21h 7.5 41h - 8.5 61h - 24.5 81h - 40.5 a1h - 56.5 c1h - 72.5 e1h - 88.5 02h 23.0 22h 7.0 42h - 9.0 62h - 25.0 82h - 41.0 a2h - 57.0 c2h - 73.0 e2h - 89.0 03h 22.5 23h 6.5 43h - 9.5 63h - 25.5 83h - 41.5 a3h - 57.5 c3h - 73.5 e3h - 89.5 04h 22.0 24h 6.0 44h - 10.0 64h - 26.0 84h - 42.0 a4h - 58.0 c4h - 74.0 e4h - 90.0 05h 21.5 25h 5.5 45h - 10.5 65h - 26.5 85h - 42.5 a5h - 58.5 c5h - 74.5 e5h - 90.5 06h 21.0 26h 5.0 46h - 11.0 66h - 27.0 86h - 43.0 a6h - 59.0 c6h - 75.0 e6h - 91.0 07h 20.5 27h 4.5 47h - 11.5 67h - 27.5 87h - 43.5 a7h - 59.5 c7h - 75.5 e7h - 91.5 08h 20.0 28h 4.0 48h - 12.0 68h - 28.0 88h - 44.0 a8h - 60.0 c8h - 76.0 e8h - 92.0 09h 19.5 29h 3.5 49h - 12.5 69h - 28.5 89h - 44.5 a9h - 60.5 c9h - 76.5 e9h - 92.5 0ah 19.0 2ah 3.0 4ah - 13.0 6ah - 29.0 8ah - 45.0 aah - 61.0 cah - 77.0 eah - 93.0 0bh 18.5 2bh 2.5 4bh - 13.5 6bh - 29.5 8bh - 45.5 abh - 61.5 cbh - 77.5 ebh - 93.5 0ch 18.0 2ch 2.0 4ch - 14.0 6ch - 30.0 8ch - 46.0 ach - 62.0 cch - 78.0 ech - 94.0 0dh 17.5 2dh 1.5 4dh - 14.5 6dh - 30.5 8dh - 46.5 adh - 62.5 cdh - 78.5 edh - 94.5 0eh 17.0 2eh 1.0 4eh - 15.0 6eh - 31.0 8eh - 47.0 aeh - 63.0 ceh - 79.0 eeh - 95.0 0fh 16.5 2fh 0.5 4fh - 15.5 6fh - 31.5 8fh - 47.5 afh - 63.5 cfh - 79.5 efh - 95.5 10h 16.0 30h 0.0 50h - 16.0 70h - 32.0 90h - 48.0 b0h - 64.0 d0h - 80.0 f0h - 96.0 11h 15.5 31h - 0.5 51h - 16.5 71h - 32.5 91h - 48.5 b1h - 64.5 d1h - 80.5 f1h - 96.5 12h 15.0 32h - 1.0 52h - 17.0 72h - 33.0 92h - 49.0 b2h - 65.0 d2h - 81.0 f2h - 97.0 13h 14.5 33h - 1.5 53h - 17.5 73h - 33.5 93h - 49.5 b3h - 65.5 d3h - 81.5 f3h - 97.5 14h 14.0 34h - 2.0 54h - 18.0 74h - 34.0 94h - 50.0 b4h - 66.0 d4h - 82.0 f4h - 98.0 15h 13.5 35h - 2.5 55h - 18.5 75h - 34.5 95h - 50.5 b5h - 66.5 d5h - 82.5 f5h - 98.5 16h 13.0 36h - 3.0 56h - 19.0 76h - 35.0 96h - 51.0 b6h - 67.0 d6h - 83.0 f6h - 99.0 17h 12.5 37h - 3.5 57h - 19.5 77h - 35.5 97h - 51.5 b7h - 67.5 d7h - 83.5 f7h - 99.5 18h 12.0 38h - 4.0 58h - 20.0 78h - 36.0 98h - 52.0 b8h - 68.0 d8h - 84.0 f8h - 100.0 19h 11.5 39h - 4.5 59h - 20.5 79h - 36.5 99h - 52.5 b9h - 68.5 d9h - 84.5 f9h - 100.5 1ah 11.0 3ah - 5.0 5ah - 21.0 7ah - 37.0 9ah - 53.0 bah - 69.0 dah - 85.0 fah - 101.0 1bh 10.5 3bh - 5.5 5bh - 21.5 7bh - 37.5 9bh - 53.5 bbh - 69.5 dbh - 85.5 fbh - 101.5 1ch 10.0 3ch - .6.0 5ch - 22.0 7ch - 38.0 9ch - 54.0 bch - 70.0 dch - 86.0 fch - 102.0 1dh 9.5 3dh - 6.5 5dh - 22.5 7dh - 38.5 9dh - 54.5 bdh - 70.5 ddh - 86.5 fdh - 102.5 1eh 9.0 3eh - 7.0 5eh - 23.0 7eh - 39.0 9eh - 55.0 beh - 71.0 deh - 87.0 feh - 103.0 1fh 8.5 3fh - 7.5 5fh - 23.5 7fh - 39.5 9fh - 55.5 bfh - 71.5 dfh - 87.5 ffh mute table 48 . adc digital volume level setting
[ak 4601 ] 016000391 - e - 0 1 - 80 - 201 6 / 12 3 . adc soft mute the adc block has a di gital soft mute circuit. the soft mute operation is performed at digital domain. the output signal is attenuated to - in att setting level x att transition time from the current adc digital volume setting level by setting ad 1 mute bit , ad2mute bit or admmute bit to 1. when the ad1mute bit, ad2mute bit or admmute bit return s to 0, the mute is cancelle d and the output attenuation level gradually changes to att setting level in att setting level x att transition time. if the soft mute is cancelled before attenuating to - after starting the operation, the attenuation is discontinued and the volume leve l return s to original volume setting l evel by the same cycle. the soft mute is effectiv e for changing the signal source without stopping the signal transmission. the attenuation level transition takes 828/fs from 0db to - and from - to 0db. soft mute function is available when each adc is in operation . the attenuation value is initialized by setting the pdn pin = l . figure 69 . adc soft mute 4 . adc input selector adc 2 of th e AK4601 ha s an input selector for 1 stereo differential input or 2 stereo single - ended input s, and 1 stereo semi - differential input . differential or single - ended input can be selected for the adcm. these inputs are selected by ad2sel[1:0] bits and admsel bi t. in the case that these registers are changed during operation, mute output signal to reduce switching noise as needed. mode ad2sel [1:0] bits selected pins 0 00 ain2lp , ain2ln , ain2rp , ain2rn (default) 1 01 ain3l , ain3r 2 10 ain4l , ain4r 3 11 ain5l , ain5r , gndin5 table 49 . adc 2 input select mode admsel bit selected pins 0 0 differential ( ainmp , ainmn ) (default) 1 1 single - ended ( ainm ) table 50 . adc m input select ad1mute , ad 2mut e , - db 0db attenuation level output image group delay ( gd ) gd 828/fs 828/fs ad mmute bit
[ak 4601 ] 016000391 - e - 0 1 - 81 - 201 6 / 12 4 - 1 . input s elector s witching s equence the input selector should be changed after enabling soft mute funct ion to reduce the switc hing noise of the input selector. adc2 in put selector switching sequence : 1) enable s oft m ute function before c hanging c hannel 2) change channel 3) disable soft mute function figure 70 . adc 2 input channel switching sequence example the period of (1) vari es according to the setting value of the datt level . transition time of attenuation level from 0db to - ? is shown below. atspad (1) period (max) lrck cycle fs=48khz fs=44.1khz fs=8khz 0 828/fs 17.25ms 18.78ms 103.5ms (default) 1 828/fs x 4 69ms 75. 10 ms 414ms t he input channel should be changed during the period (2). an interval around 200ms is needed before releasing the soft mute after changing the channel (period (3)). 5 . adc digital filter select the AK4601 ha s four kinds of digital filters in adc block. adsd and adsl bits select a digital filter. mode adsd bit adsl bit digital filter 0 0 0 sharp roll - off filter (default) 1 0 1 slow roll - off filter 2 1 0 short delay sharp roll - off filter 3 1 1 short delay slow roll - off filter table 51 . adc digital filter select 6 . ad c full scale voltage single - ended input amplitude (differential input amplitude) of adc1 l/rch, adc2 l/rch and adcm can be switched between 2.3vpp ( 2.3vpp) and 2.83vpp ( 2.83vpp) by adc1vl/r bit, adc2v l /r bit and adcmv bit , respectively ( table 52 ). mode adc1v l , adc1v r , adc2vl, adc2vr , adcmv full scale single - end differential 0 0 2.3vpp attenuation channel datt level - (1) (2) in 3 l/in 3 r in 4 l/in 4 r (1) (3) ad 2 mute bit
[ak 4601 ] 016000391 - e - 0 1 - 82 - 201 6 / 12 dac block ( dac1 , dac2 and dac3 ) 1 . dac d i gital volume th e AK4601 has c hannel - independent digital volume controls in dac block . (256 levels, 0.5 steps) dac 1 lch volda 1 l[7:0] dac 1 r ch volda 1r [7:0] dac 2 lch volda 2 l[7:0] dac 2 rch volda 2 r[7:0] dac 3 lch volda 3 l[7:0] dac 3 rch volda 3 r[7:0] attenuation level 00h 00h 00h 00h 00h 00h +12.0db 01h 01h 01h 01h 01h 01h +11.5db 02h 02h 02h 02h 02h 02h +11.0db : : : : : : : 17h 17h 17h 17h 17h 17h +0.5db 18h 18h 18h 18h 18h 18h 0.0db (default) 19h 19h 19h 19h 19h 19h - 0.5db : : : : : : : fdh fdh fdh fdh fdh fdh - 114.5db feh feh feh feh feh feh - 115.0db ffh ffh ffh ffh ffh ffh mute ( - ) table 53 . dac digital volume setting transition time between set values can be selected by atspda bit. mode atsp da att speed 0 0 4/fs (default) 1 1 16/fs table 54 . dac volume transition time setting when changing output levels, transitions are executed via soft changes; thus no switching noise occurs during these transitions. in mode 0, i t takes 102 0 /fs ( 21 .3ms@fs=48khz) from 00h(0db) to ffh(mute). if the pdn pin goes to l, each channel of the dac is initialized to 18 h. atsp da 00h ?
[ak 4601 ] 016000391 - e - 0 1 - 83 - 201 6 / 12 table 56 . dac digital volume level setting 2 . dac soft mute the dac block has a digital soft mute circuit. the soft mute operation is performed at digital domain. the output signal is attenuated to - in att setting level x att transition time from the current dac digital volume setting level by setting da1 mute bit , da2mute bit or da3mute bit to 1. when the da 1mute bit , da 2mute bit or da3 mute bit return s to 0, the mute is cancelled and the output attenuation level gradually changes to att setting level in att setting level x att transition time. if the soft mute is cancelled before attenuating to - after starting the operation, the attenuation is discontinued and the volume level return s to original volume settin g level by the same cycle. the soft mute is effective for changing the signal source without stopping the signal transmission. the attenuation level transition takes 924/fs from 0db to - and from - to 0db. soft mute function is available when each dac i s in operation . the attenuation value is initialized by setting the pdn pin = l . code db code db code db code db code db code db code db code db 00h 12.0 20h - 4.0 40h - 20.0 60h - 36.0 80h - 52.0 a0h - 68.0 c0h - 84.0 e0h - 100.0 01h 11. 5 21h - 4.5 41h - 20.5 61h - 36.5 81h - 52.5 a1h - 68.5 c1h - 84.5 e1h - 100.5 02h 11.0 22h - 5.0 42h - 21.0 62h - 37.0 82h - 53.0 a2h - 69.0 c2h - 85.0 e2h - 101.0 03h 10.5 23h - 5.5 43h - 21.5 63h - 37.5 83h - 53.5 a3h - 69.5 c3h - 85.5 e3h - 101.5 04h 10.0 24h - .6.0 44h - 22.0 64h - 38.0 84h - 54.0 a4h - 70.0 c4h - 86.0 e4h - 102.0 05h 9.5 25h - 6.5 45h - 22.5 65h - 38.5 85h - 54.5 a5h - 70.5 c5h - 86.5 e5h - 102.5 06h 9.0 26h - 7.0 46h - 23.0 66h - 39.0 86h - 55.0 a6h - 71.0 c6h - 87.0 e6h - 103.0 07h 8.5 27h - 7.5 47h - 23.5 67h - 39.5 87h - 55.5 a7h - 71.5 c7h - 87.5 e7h - 103.5 08h 8.0 28h - 8.0 48h - 24.0 68h - 40.0 88h - 56.0 a8h - 72.0 c8h - 88.0 e8h - 104.0 09h 7.5 29h - 8.5 49h - 24.5 69h - 40.5 89h - 56.5 a9h - 72.5 c9h - 88.5 e9h - 104.5 0ah 7.0 2ah - 9.0 4ah - 25.0 6ah - 41.0 8ah - 57.0 aah - 73.0 cah - 89.0 eah - 105.0 0bh 6.5 2bh - 9.5 4bh - 25.5 6bh - 41.5 8bh - 57.5 abh - 73.5 cbh - 89.5 ebh - 105.5 0ch 6.0 2ch - 10.0 4ch - 26.0 6ch - 42.0 8ch - 58.0 ach - 74.0 cch - 90.0 ech - 106.0 0dh 5.5 2dh - 10.5 4dh - 26.5 6dh - 42.5 8dh - 58.5 adh - 74.5 cdh - 90.5 edh - 106.5 0eh 5.0 2eh - 11.0 4eh - 27.0 6eh - 43.0 8eh - 59.0 aeh - 75.0 ceh - 91.0 eeh - 107.0 0fh 4.5 2fh - 11.5 4fh - 27.5 6fh - 43.5 8fh - 59.5 afh - 75.5 cfh - 91.5 efh - 107.5 10h 4.0 30h - 12.0 50h - 28.0 70h - 44.0 90h - 60.0 b0h - 76.0 d0h - 92.0 f0h - 108.0 11h 3.5 31h - 12.5 51h - 28.5 71h - 44.5 91h - 60.5 b1h - 76.5 d1h - 92.5 f1h - 108.5 12h 3.0 32h - 13.0 52h - 29.0 72h - 45.0 92h - 61.0 b2h - 77.0 d2h - 93.0 f2h - 109.0 13h 2.5 33h - 13.5 53h - 29.5 73h - 45.5 93h - 61.5 b3h - 77.5 d3h - 93.5 f3h - 109.5 14h 2.0 34h - 14.0 54h - 30.0 74h - 46.0 94h - 62.0 b4h - 78.0 d4h - 94.0 f4h - 110.0 15h 1.5 35h - 14.5 55h - 30.5 75h - 46.5 95h - 62.5 b5h - 78.5 d5h - 94.5 f5h - 110.5 16h 1.0 36h - 15.0 56h - 31.0 76h - 47.0 96h - 63.0 b6h - 79.0 d6h - 95.0 f6h - 111.0 17h 0.5 37h - 15.5 57h - 31.5 77h - 47.5 97h - 63.5 b7h - 79.5 d7h - 95.5 f7h - 111.5 18h 0.0 38h - 16.0 58h - 32.0 78h - 48.0 98h - 64.0 b8h - 80.0 d8h - 96.0 f8h - 112.0 19h - 0.5 39h - 16.5 59h - 32.5 79h - 48.5 99h - 64.5 b9h - 80.5 d9h - 96.5 f9h - 112.5 1ah - 1.0 3ah - 17.0 5ah - 33.0 7ah - 49.0 9ah - 65.0 bah - 81.0 dah - 97.0 fah - 113.0 1bh - 1.5 3bh - 17.5 5bh - 33.5 7bh - 49.5 9bh - 65.5 bbh - 81.5 dbh - 97.5 fbh - 113.5 1ch - 2.0 3ch - 18.0 5ch - 34.0 7ch - 50.0 9ch - 66.0 bch - 82.0 dch - 98.0 fch - 114.0 1dh - 2.5 3dh - 18.5 5dh - 34.5 7dh - 50.5 9dh - 66.5 bdh - 82.5 ddh - 98.5 fdh - 114.5 1eh - 3.0 3eh - 19.0 5eh - 35.0 7eh - 51.0 9eh - 67.0 beh - 83.0 deh - 99.0 feh - 115.0 1fh - 3.5 3fh - 19.5 5fh - 35.5 7fh - 51.5 9fh - 67.5 bfh - 83.5 dfh - 99.5 ffh mute
[ak 4601 ] 016000391 - e - 0 1 - 84 - 201 6 / 12 figure 71 . dac sof mute operation the analog output pin will be in a mode that output s vcom voltage by changing hresetn pin to 0 from 1 while pmda bit = 1 when changing system clock during dac operation. this mode can prevent a click noise when the dac resumes operation after changing the system clock ( figure 72 , case1). the analog output will be hi - z state when changing hresetn to 0 from 1 while pmda bit = 0 . a click noise may occur when resuming the dac operation after the system clock is changed ( figure 72 , case2). figure 72 . analog output in hub reset 3 . dac digital filter select t h e AK4601 has four kinds of digital filters in dac block. dasd and dasl bits select a digital filter. mode dasd bit dasl bit digital filter 0 0 0 sharp roll - off filter 1 0 1 slow roll - off filter 2 1 0 short delay sharp roll - off filter (default) 3 1 1 short delay slow roll - off filter table 57 . dac digital filter select 4 . de - emphasis f i lter control the AK4601 h as a digital de - emphasis filter (tc=50/15s) which correspond s to three sampling frequencies (32khz, 44.1khz, 48khz) by iir filter. i t is enabled or disabled with the dem x[ 1 : 0 ] bits (x=1~3) ( table 58 ) . da 1 /2/3 mute bit - db 0db attenuation level output image 924/fs 924/fs group delay ( gd ) gd soft mute operation h reset n bit pmda x bit 1 analog output vcom output vcom output case1 case2 pmda x bit 0 analog output vcom output vcom output vcom output hiz
[ak 4601 ] 016000391 - e - 0 1 - 85 - 201 6 / 12 demx[1] bit demx[0] bit mode 0 0 44.1khz 0 1 off (default) 1 0 48khz 1 1 32khz table 58 . de - emphasis filter control the de - emphasis filer only corresponds to the frequencies shown in table 58 . demx[1:0] bits must be set to the default setting 01 when the AK4601 is operated with other sampling frequencies. ? in the case that the AK4601 is operated with a sampling frequency other than shown in table 58 . the frequency characteristics of the de - emphasis filter will track the sampling frequency of the actual operation . (e.g. the cut - off frequency exists around 1khz in 48khz mode, around 2khz in 96khz mode and around 0.5khz in 24khz mode.)
[ak 4601 ] 016000391 - e - 0 1 - 86 - 201 6 / 12 register map control registers can be initialized by a power - down release (pdn pin = l h ). do not write to registers in the address after 00 8c h and write "0 " into 0 bits and write "1" into 1 bit . normal registers addr [hex] register name d7 d6 d5 d4 d3 d2 d1 d0 default 00 00 system clock setting 1 refsel[2:0] refmode[4:0] 00 0001 system clock setting 2 ckresetn 0 0 fsmode[4:0] 00 00 02 mic bias power management psw1n psw2n 0 0 0 0 pmmb1 pmmb2 00 00 03 sync domain 1 setting 1 msn1 cks1[2:0] bdv1[8] sdv1[2:0] 00 00 04 sync domain 1 setting 2 bdv1[7:0] 00 00 05 sync domain 2 setting 1 msn2 cks2[2:0] bdv2[8] sdv2[2:0] 00 00 06 sync domain 2 setting 2 bdv2[7:0] 00 00 07 reserved 0 00 00 08 reserved 0 00 00 09 reserved 0 00 00 0a reserved 0 00 00 0b reserved 0 00 00 0c reserved 0 00 000d reserved 0 00 000e reserved 0 00 000f clko output setting 0 0 0 0 clkoe clkosel[2:0] 00 0010 pin setting 0 0 0 0 0 0 0 mseln 00 0011 sync domain select 1 0 sdbck1[2:0] 0 sdbck2[2:0] 00 00 1 2 reserved 0 00 0013 sync domain select 3 0 0 0 0 0 exbck1[2:0] 00 00 1 4 sync domain select 4 0 exbck2[2:0] 0 exbck3[2:0] 00 00 1 5 reserved 0 00 00 1 6 sync domain select 6 0 sddo1[2:0] 0 sddo2[2:0] 00 00 1 7 sync domain select 7 0 sddo3[2:0] 0 0 0 0 00 00 1 8 sync domain select 8 0 0 0 0 0 sdvol1[2:0] 00 00 1 9 sync domain select 9 0 sdvol2[2:0] 0 sdvol3[2:0] 00 001a reserved 0 00 001b reserved 0 00 001c reserved 0 00 001d reserved 0 00 001e reserved 0 00 001f sync domain select 15 0 sdmixa[2:0] 0 sdmixb[2:0] 00 00 2 0 sync domain select 16 0 sdadc1[2:0] 0 sdcodec[2:0] 00 00 2 1 sdout1 tdm slot1 - 2 d ata select 0 0 seldo1a[5:0] 00 00 2 2 sdout1 tdm slot3 - 4 d ata select 0 0 seldo1b[5:0] 00 00 2 3 sdout1 tdm slot5 - 6 d ata select 0 0 seldo1c[5:0] 00 00 2 4 sdout1 tdm slot7 - 8 d ata select 0 0 seldo1d[5:0] 00 00 2 5 sdout1 tdm slot9 - 10 d ata select 0 0 seldo1e[5:0] 00 00 2 6 sdout1 tdm slot11 - 12 d ata select 0 0 seldo1f[5:0] 00 00 2 7 sdout1 tdm slot13 - 14 d ata select 0 0 seldo1g[5:0] 00 00 2 8 sdout1 tdm slot15 - 16 d ata select 0 0 seldo1h[5:0] 00 00 2 9 sdout2 output data select 0 0 seldo2[5:0] 00 00 2 a sdout3 output data select 0 0 seldo3[5:0] 00 00 2 b reserved 0 00 00 2 c reserved 0 00 00 2 d reserved 0 00 00 2 e reserved 0 00 00 2 f reserved 0 00 0030 reserved 0 00 0031 reserved 0 00
[ak 4601 ] 016000391 - e - 0 1 - 87 - 201 6 / 12 addr [hex] register name d7 d6 d5 d4 d3 d2 d1 d0 default 0032 reserved 0 00 0033 reserved 0 00 0034 reserved 0 00 0035 dac1 input data select 0 0 selda1[5:0] 00 0036 dac2 input data select 0 0 selda2[5:0] 00 0037 dac 3 input data select 0 0 selda 3 [5:0] 00 0038 vol1 input data s elect 0 0 selvol1[5:0] 00 00 39 vol2 input data s elect 0 0 selvol2[5:0] 00 00 3a vol3 input data s elect 0 0 selvol3[5:0] 00 00 3 b reserved 0 00 003c reserved 0 00 003d reserved 0 00 003e reserved 0 00 003f reserved 0 00 0040 reserved 0 00 0041 reserved 0 00 0042 reserved 0 00 0043 reserved 0 00 0044 reserved 0 00 0045 mixer a ch1 input data select 0 0 selmixai1[5:0] 00 0046 mixer a ch2 input data select 0 0 selmixai2[5:0] 00 0047 mixer b ch1 input data select 0 0 selmixbi1[5:0] 00 0048 mixer b ch2 input data select 0 0 selmixbi2[5:0] 00 0049 reserved 0 00 004a reserved 0 00 004b reserved 0 00 00 4 c clock format setting 1 bckp1 dcf1[2:0] bckp2 dcf2[2:0] 00 00 4 d reserved 0 00 00 4 e reserved 0 00 00 4 f reserved 0 00 0050 sdin1 digital input format diedgen1 0 disl1[1:0] dilsbe1 0 didl1[1:0] 00 0051 sdin2 digital input format diedgen2 0 disl2[1:0] dilsbe2 0 didl2[1:0] 00 0052 sdin3 digital input format diedgen3 0 disl3[1:0] dilsbe3 0 didl3[1:0] 00 00 5 3 reserved 0 00 00 5 4 reserved 0 00 0055 sdout1 digital output format doedgen1 0 dosl1[1:0] dolsbe1 0 dodl1[1:0] 00 0056 sdout2 digital output format doedgen2 0 dosl2[1:0] dolsbe2 0 dodl2[1:0] 00 00 5 7 sdout3 digital output format doedgen3 0 dosl3[1:0] dolsbe3 0 dodl3[1:0] 00 00 5 8 reserved 0 00 00 5 9 reserved 0 00 005a sdout phase setting 0 0 0 0 0 sdoph3 sdoph2 sdoph1 00 00 5 b reserved 0 00 005c reserved 0 00 005d reserved 0 00 005e output port enable setting 0 0 sdout1e sdout2e sdout3e 0 0 0 00 005f reserved 0 00 0060 mixer a setting sfta2[1: 0 ] sfta1[1:0] swpa2[1:0] swpa1[1:0] 00 0061 mixer b setting sftb2[1:0] sftb1[1:0] swpb2[1:0] swpb1[1:0] 00 0062 mic amp gain mgnl[ 3 :0] mgnr[ 3 :0] 00 0063 analog input gain control adc1vl adc1vr adc2vl adc2vr adcmv 0 mic l zce mic r zce 00 0064 adc1 lch digital volume volad1l[7:0] 30 0065 adc1 rch digital volume volad1r[7:0] 30 0066 adc2 lch digital volume volad2l[7:0] 30 0067 adc2 rch digital volume volad2r[7:0] 30 0068 adcm digital volume voladm[7:0] 30 0069 reserved 0 00 006a reserved 0 00
[ak 4601 ] 016000391 - e - 0 1 - 88 - 201 6 / 12 addr [hex] register name d7 d6 d5 d4 d3 d2 d1 d0 default 00 6 b analog input select setting adsd adsl 0 admsel ad1lsel ad1rsel ad2sel[1:0] 00 00 6 c adc mute & hpf control atspad ad1mute ad2mute admmute 0 ad1hpfn ad2hpfn ad m hpfn 00 00 6 d dac1 lch digital volume volda1l[7:0] 18 00 6 e dac1 rch digital volume volda1r[7:0] 18 00 6 f dac2 lch digital volume volda2l[7:0] 18 0070 dac2 rch digital volume volda2r[7:0] 18 00 71 dac 3 lch digital volume volda 3 l[7:0] 18 00 72 dac 3 rch digital volume volda 3 r[7:0] 18 00 73 dac mute & filter setting atspda da1mute da2mute da3mute 0 dsmn dasd dasl 02 00 74 dac dem setting 0 0 dem3[1:0] dem2[1:0] dem1[1:0] 15 00 75 vol 1 lch digital volume vol1l[ 7 :0] 18 00 76 vol 1 r ch digital volume vol1 r [ 7 :0] 18 00 77 vol2 lch digital volume vol 2 l[ 7 :0] 18 00 78 vol2 r ch digital volume vol 2r [ 7 :0] 18 00 79 vol3 lch digital volume vol 3 l[ 7 :0] 18 00 7a vol3 r ch digital volume vol 3r [ 7 :0] 18 007b reserved 0 0 0 1 1 0 0 0 18 007c reserved 0 0 0 1 1 0 0 0 18 007d reserved 0 0 0 1 1 0 0 0 18 007e reserved 0 0 0 1 1 0 0 0 18 007f vol setting atspvol 0 0 0 0 0 0 0 00 0080 reserved 0 00 0081 reserved 0 00 0082 reserved 0 00 0083 sto flag setting 1 0 plllocke 0 0 0 0 0 0 00 0084 reserved 0 00 0085 reserved 0 00 0086 reserved 0 0 0 0 0 1 0 0 04 0087 reserved 0 0 0 0 0 0 1 0 02 0088 reserved 0 00 0089 reserved 0 00 008a power management 1 0 0 pmad1 pmad2 pmadm pmda1 pmda2 pmda3 00 008b reserved 0 00 008c reset control 0 0 1 cresetn 0 0 0 hresetn 2 0 read o nly registers read these registers after clock reset is released (when pll is stabilized). addr [hex] register name d7 d6 d5 d4 d3 d2 d1 d0 default 0100 reserved 0 00 0101 reserved 0 00 0102 status read out 0 sto 0 0 0 0 0 0 40
[ak 4601 ] 016000391 - e - 0 1 - 89 - 201 6 / 12 register definitions normal registers addr register name d7 d6 d5 d4 d3 d2 d1 d0 00 00 system clock setting 1 refsel[ 2 :0] refmode[4:0] r/w r/w r/w default 000 00h refsel[3:0]: pll reference clock input pin setting ( table 4 ) default: 000 ( mcki ) refmode[4:0]: pll reference clock frequency setting ( table 5 ) default: 00h ( 256khz ) addr register name d7 d6 d5 d4 d3 d2 d1 d0 0001 system clock setting 2 ckresetn 0 fsmode[4:0] r/w r/w r/w r/w r/w default 0 0 0 00h ckresetn: clock reset 0: clock reset (default) 1: clock reset release fsmode[4:0]: operation sampling frequency mode setting for each block ( table 12 ) default: 00h (8khz) addr register name d7 d6 d5 d4 d3 d2 d1 d0 0002 mic bias power management psw1n psw2n 0 pmmb 1 pmmb2 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 psw1n: pull - down setting for bick1pin / lrck1 pin ( table 2 ) 0: pulled down (46k ) (default) 1: release psw2n: pull - down setting for bick2 pin/ lrck2 pin ( table 2 ) 0: pulled down (46k ) (default) 1: release pmmb1: power management setting for mic bias output 1 0: power s a ve mode (default) 1: normal operation pmmb2: power management setting for mic bias output 2 0: power s a ve mode (default) 1: normal operation
[ak 4601 ] 016000391 - e - 0 1 - 90 - 201 6 / 12 addr register name d7 d6 d5 d4 d3 d2 d1 d0 00 03 sync domain 1 setting 1 msn1 cks1[2:0] bdv1[ 8 ] sdv1[2:0] 00 04 sync domain 1 setting 2 bdv1[7:0] r/w r/w r/w r/w r/w default 0 000 0 000 msn1: slave/master mode setting for bick1 pin/lrck1 pin ( table 16 ) 0: slave mode (default) 1: master mode cks1[2:0]: mbick1 d ivider reference clock setting of clock sync domain 1 ( table 8 ) default: 000 (tielow) bdv1[8:0]: mbick1 divider setting ( table 9 ) default: 0 0 0h ( divided by 1 ) sdv1[2:0]: mlrck1 di vider setting ( table 10 ) default: 000 ( divided by 64 ) addr register name d7 d6 d5 d4 d3 d2 d1 d0 00 0 5 sync domain 2 setting 1 msn 2 cks 2 [2:0] bdv 2 [ 8 ] sdv 2 [2:0] 00 0 6 sync domain 2 setting 2 bdv 2 [7:0] r/w r/w r/w r/w r/w default 0 000 0 000 msn 2 : slave/master mode setting for bick 2 pin/lrck 2 pin ( table 16 ) 0: slave mode (default) 1: master mode cks 2 [2:0]: mbick 2 d ivider reference clock setting of clock sync domain 2 ( table 8 ) default: 000 (tielow) bdv 2 [8:0]: mbick 2 divider setting ( table 9 ) default: 0 0 0h ( divided by 1 ) sdv 2 [2:0]: mlrck 2 di vider setting ( table 10 ) default: 000 (divided by 64) addr register name d7 d6 d5 d4 d3 d2 d1 d0 00 0f clko output setting 0 clkoe clkosel[2:0] r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 000 clkoe: clko pin output enable 0: clko pin = l (default) 1: clko output enable clkosel[2:0]: clko pin output clock frequency setting ( table 13 ) default: 000 (12.288mhz / 11.2896mhz)
[ak 4601 ] 016000391 - e - 0 1 - 91 - 201 6 / 12 addr register name d7 d6 d5 d4 d3 d2 d1 d0 0010 pin setting 0 mseln r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 mseln: bick2/sdin3 pin and lrck2/sdout3 pin setting 0: bick 2 pin, lrck 2 pin (default) 1: sdin3 pin, sdout3 pin addr register name d7 d6 d5 d4 d3 d2 d1 d0 0011 sync domain select 1 0 sdbck1[2:0] 0 sdbck2[2:0] 0013 sync domain select 3 0 exbck1[2:0] 0014 sync domain select 4 0 exbck2[2:0] 0 exbck3[2:0] 0016 sync domain select 6 0 sddo1[2:0] 0 sddo2[2:0] 0017 sync domain select 7 0 sddo3[2:0] 0 0018 sync domain select 8 0 sdvol1[2:0] 0019 sync domain select 9 0 sdvol2[2:0] 0 sdvol3[2:0] 001f sync domain select 15 0 sdmixa[2:0] 0 sdmixb[2:0] 0020 sync domain select 16 0 sdadc1[2:0] 0 sdcodec[2:0] r/w r/w r/w r/w r/w default 0 000 0 000 sdxxxx[2:0]: clock sync domain setting for input/output port ( table 20 , table 21 ) default: 000 (not assigned) exbckx[2:0]: sdinx pin symchronizing clock select ( table 15 ) default: 000 (not assigned)
[ak 4601 ] 016000391 - e - 0 1 - 92 - 201 6 / 12 addr register name d7 d6 d5 d4 d3 d2 d1 d0 0021 sdout1 tdm slot1 - 2 d ata select 0 seldo1a[5:0] 0022 sdout1 tdm slot3 - 4 d ata select 0 seldo1b[5:0] 0023 sdout1 tdm slot5 - 6 d ata select 0 seldo1c[5:0] 0024 sdout1 tdm slot7 - 8 d ata select 0 seldo1d[5:0] 0025 sdout1 tdm slot9 - 10 d ata select 0 seldo1e[5:0] 0026 sdout1 tdm slot11 - 12 d ata select 0 seldo1f[5:0] 0027 sdout1 tdm slot13 - 14 d ata select 0 seldo1g[5:0] 0028 sdout1 tdm slot15 - 16 d ata select 0 seldo1h[5:0] 0029 sdout2 output data select 0 seldo2[5:0] 002a sdout3 output data select 0 seldo3[5:0] 0035 dac1 input data select 0 selda1[5:0] 0036 dac2 input data select 0 selda2[5:0] 0037 dac3 input data select 0 selda3[5:0] 0038 vol1 input data select 0 selvol1[5:0] 0039 vol2 input data select 0 selvol2[5:0] 003a vol3 input data select 0 selvol3[5:0] 0045 mixer a ch1 input data select 0 selmixai1[5:0] 0046 mixer a ch2 input data select 0 selmixai2[5:0] 0047 mixer b ch1 input data select 0 selmixbi1[5:0] 0048 mixer b ch2 input data select 0 selmixbi2[5:0] r/w r/w r/w r/w default 0 0 00h selxxx[5:0]: data source select of output port ( table 21 ) default: 00h ( all0 )
[ak 4601 ] 016000391 - e - 0 1 - 93 - 201 6 / 12 addr register name d7 d6 d5 d4 d3 d2 d1 d0 00 4c clock format setting 1 bckp1 dcf1[2:0] bckp2 dcf2[2:0] r/w r/w r/w r/w r/w default 0 000 0 000 bckp1: relationship of lrck1 and bick1 edges ( table 23 ) 0: lrck1 starts on a bick1 falling edge (default) 1: lrck1 starts on a bick1 rising edge dcf1 [2:0]: lrck1/bick1 clock format setting ( table 22 ) default: 000 ( i 2 s mode) bckp2: relationship of lrck2 and bick2 edges ( table 23 ) 0: lrck2 starts on a bick2 falling edge (default) 1: lrck2 starts on a bick2 rising edge dcf2[2:0]: lrck2/bick2 clock format setting ( table 22 ) default: 000 ( i 2 s mode) addr register name d7 d6 d5 d4 d3 d2 d1 d0 00 50 sdin1 digital input format diedgen1 0 disl1[1:0] dilsbe1 0 didl1[1:0] r/w r/w r/w r/w r/w r/w r/w default 0 0 00 0 0 00 diedgen1: start timing setting of data transferring for second and succeeding channels of sdin1 0: lrck edge basis (default) 1: slot length basis disl1[1:0]: sdin1 data slot length setting ( table 24 ) defau lt: 00 (24 bit) dilsbe1: msb/lsb setting of audio data in data slot of sdin1 0: msb (default) 1: lsb didl1[1:0]: audio data word length setting of sdin1 ( table 25 ) defaul t: 00 (24bi t) addr register name d7 d6 d5 d4 d3 d2 d1 d0 00 51 sdin2 digital input format diedgen2 0 disl2[1:0] dilsbe2 0 didl2[1:0] r/w r/w r/w r/w r/w r/w r/w default 0 0 00 0 0 00 diedgen2: start timing setting of data transferring for second and succeeding channels of sdin2 0: lrck edge basis (default) 1: slot length basis disl2[1:0]: sdin2 data slot length setting ( table 24 ) default : 00 (2 4bit) dilsbe2: msb/lsb setting of audio data in data slot of sdin2 0: msb (default) 1: lsb didl2[1:0]: audio data word length setting of sdin2 ( table 25 ) default : 00 (24 bit)
[ak 4601 ] 016000391 - e - 0 1 - 94 - 201 6 / 12 addr register name d7 d6 d5 d4 d3 d2 d1 d0 00 52 sdin3 digital input format diedgen3 0 disl3[1:0] dilsbe3 0 didl3[1:0] r/w r/w r/w r/w r/w r/w r/w default 0 0 00 0 0 00 diedgen3: start timing setting of data transferring for second and succeeding channels of sdin3 0: lrck edge basis (default) 1: slot length basis disl3[1:0]: sdin3 data slot length setting ( table 24 ) default: 00 (24bit ) dilsbe3: msb/lsb setting of audio data in data slot of sdin3 0: msb (default) 1: lsb didl3[1:0]: audio data word length setting of sdin3 ( table 25 ) defau lt: 00 (2 4bit) addr register name d7 d6 d5 d4 d3 d2 d1 d0 00 55 sdout1 digital output format doedgen1 0 dosl1[1:0] dolsbe1 0 dodl1[1:0] r/w r/w r/w r/w r/w r/w r/w default 0 0 00 0 0 00 doedgen1: start timing setting of data transferring for second and succeeding channels of sdout1 0: lrck edge basis (default) 1: slot length basis dosl1[1:0]: sdout1 data slot length setting ( table 24 ) defaul t: 00 (24b it) dolsbe1: msb/lsb setting of audio data in data slot of sdout1 0: msb (default) 1: lsb dodl1[1:0]: audio data word length setting of sdout1 ( table 25 ) default: 00 (2 4bit) addr register name d7 d6 d5 d4 d3 d2 d1 d0 00 56 sdout2 digital output format doedgen2 0 dosl2[1:0] dolsbe2 0 dodl2[1:0] r/w r/w r/w r/w r/w r/w r/w default 0 0 00 0 0 00 doedgen 2 : start timing setting of data transferring for second and succeeding channels of sdout 2 0: lrck edge basis (default) 1: slot length basis dosl 2 [1:0]: sdout 2 data slot length setting ( table 24 ) default : 00 (24bit) dolsbe 2 : msb/lsb setting of audio data in data slot of sdout 2 0: msb (default) 1: lsb dodl 2 [1:0]: audio data word length setting of sdout 2 ( table 25 ) default: 00 (24 bit)
[ak 4601 ] 016000391 - e - 0 1 - 95 - 201 6 / 12 addr register name d7 d6 d5 d4 d3 d2 d1 d0 00 57 sdout3 digital output format doedgen3 0 dosl3[1:0] dolsbe3 0 dodl3[1:0] r/w r/w r/w r/w r/w r/w r/w default 0 0 00 0 0 00 doedgen 3 : start timing setting of data transferring for second and succeeding channels of sdout 3 0: lrck edge basis (default) 1: slot length basis dosl 3 [1:0]: sdout 3 data slot length setting ( table 24 ) default: 00 ( 24bit) dolsbe 3 : msb/lsb setting of audio data in data slot of sdout 3 0: msb (default) 1: lsb dodl 3 [1:0]: audio data word length setting of sdout 3 ( table 25 ) default: 00 ( 24bit) addr register name d7 d6 d5 d4 d3 d2 d1 d0 00 5a sdout phase setting 0 sdoph3 sdoph2 sdoph1 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 sdoph3: high speed mode setting for sdout3 in slave mode ( note 41 ) 0: normal mode (default) 1: high speed mode sdoph2: high speed mode setting for s dout2 in slave mode ( note 41 ) 0: normal mode (default) 1: high speed mode sdoph1: high speed mode setting for sdout1 in slave mode ( note 41 ) 0: normal mode (default) 1: high speed mode addr register name d7 d6 d5 d4 d3 d2 d1 d0 00 5e output port enable setting 0 sdout1e sdout2e sdout3e 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 sdout1e: sdout1 output enable 0: sdout1 pin = l (default) 1: sdout1 output enable sdout2e: sdout2 output enable 0: sdout2 pin = l (default) 1: sdout2 output enable sdout3e: sdout3 output enable 0: sdout3 pin = l (default) 1: sdout3 output enable
[ak 4601 ] 016000391 - e - 0 1 - 96 - 201 6 / 12 addr register name d7 d6 d5 d4 d3 d2 d1 d0 00 60 mixer a setting sfta2[1:0] sfta1[1:0] swpa2[1:0] swpa1[1:0] r/w r/w r/w r/w r/w default 00 00 00 00 sfta2[1:0]: level adjustment function setting for input2 of mixer a ( table 34 ) default: 00 ( not shifted ) sfta1[1:0]: level adjustment function setting for input1 of mixer a ( table 34 ) default: 00 (not shifted) swpa2[1:0]: data change setting for input 2 of mixer a ( table 35 ) default: 00 (through) swpa1[1:0]: data change setting for input 1 of mixer a ( table 35 ) default: 00 (through) addr register name d7 d6 d5 d4 d3 d2 d1 d0 00 61 mixer b setting sft b 2[1:0] sft b 1[1:0] swp b 2[1:0] swp b 1[1:0] r/w r/w r/w r/w r/w default 00 00 00 00 sftb2[1:0]: level adjustment function setting for input2 of mixer b ( table 34 ) default: 00 (not shifted) sftb1[1:0]: level adjustment function setting for input1 of mixer b ( table 34 ) default: 00 (not shifted) swpb2[1:0]: data change setting for input 2 of mixer b ( table 35 ) default: 00 (through) swpb1[1:0]: data change setting for input 1 of mixer b ( table 35 ) default: 00 (through) addr register name d7 d6 d5 d4 d3 d2 d1 d0 00 62 mic amp gain mgnl[3:0] mgnr[3:0] r/w r/w r/w default 0000 0000 mgnl[3:0]: mic input lch gain setting ( table 40 ) default: 0h ( 0db) mgnr[3:0]: mic input rch gain setting ( table 40 ) default: 0h (0 db)
[ak 4601 ] 016000391 - e - 0 1 - 97 - 201 6 / 12 addr register name d7 d6 d5 d4 d3 d2 d1 d0 00 63 analog input gain control adc1vl adc1vr adc2vl adc2vr adcmv 0 mic l zce mic r zce r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 adc1vl: lch input voltage setting of adc1 ( table 52 ) default: 0 (2.3vpp( 2.3vpp)) adc1vr: rch input voltage setting of adc1 ( table 52 ) default: 0 (2.3vpp( 2.3vpp)) adc2vl: lch input voltage setting of adc2 ( table 52 ) default: 0 (2.3vpp( 2.3vpp)) adc2vr: rch input voltage setting of adc2 ( table 52 ) default: 0 (2.3vpp( 2.3vpp)) adcmv: input voltage setting of adcm ( table 52 ) default: 0 (2.3vpp( 2.3vpp)) miclzce: mic gain zero crossing enable for lch 0: lch zero crossing detection is off (default) 1: lch zero crossing detection is on micrzce: mic gain zero crossing enable for rch 0: r ch zero crossing detection is off (default) 1: r ch zero crossing detection is on addr register name d7 d6 d5 d4 d3 d2 d1 d0 00 64 adc1 lch digital volume volad1l[7:0] 00 65 adc1 rch digital volume volad1r[7:0] 00 66 adc2 lch digital volume volad2l[7:0] 00 67 adc2 rch digital volume volad2r[7:0] 00 68 adcm digital volume voladm[7:0] r/w r/w default 30h volad1l[7:0]: lch digital volume setting of adc1 ( table 45 ) default: 30h (0db) volad1r[7:0]: rch digital volume setting of adc1 ( table 45 ) default: 30h (0db) volad2l[7:0]: lch digital volume setting of adc2 ( table 45 ) default: 30h (0db) volad2r[7:0]: rch digital volume setting of adc2 ( table 45 ) default: 30h (0db) voladm[7:0]: digital volume setting of adcm ( table 45 ) default: 30h (0db)
[ak 4601 ] 016000391 - e - 0 1 - 98 - 201 6 / 12 addr register name d7 d6 d5 d4 d3 d2 d1 d0 00 6b analog input select setting adsd adsl 0 admsel ad1lsel ad1rsel ad2sel[1:0] r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 00 adsd, adsl: adc digital filter select ( table 51 ) 00: sharp roll - off filter (default) 01: slow roll - off filter 10: short delay sharp roll - off filter 11: short delay slow roll - off filter admsel: adcm input pin select ( table 50 ) 0: ainmp, ainmn (default) 1: ainmp ad1lsel: adc1 lch input pin select ( table 42 ) 0: inp1/inn 1 (default) 1: ain1l ad1rsel: adc1 rch input pin select ( table 42 ) 0: inp 2 /inn 2 (default) 1: ain1r ad2sel[1:0]: adc2 input pin select ( table 49 ) default: 00 (ain2lp , ain2ln , ain2rp , ain2rn)
[ak 4601 ] 016000391 - e - 0 1 - 99 - 201 6 / 12 addr register name d7 d6 d5 d4 d3 d2 d1 d0 00 6c adc mute & hpf control atspad ad1mute ad2mute admmute 0 ad1hpfn ad2hpfn ad m hpfn r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 atspad: adc digital volume transition time setting ( table 46 ) 0: 4 /fs (default) 1: 16 /fs ad1mute: adc1 soft mute enable 0: soft mute disable (default) 1: soft mute enable ad2mute: adc2 soft mute enable 0: soft mute disable (defaul t) 1: soft mute enable admmute: adcm soft mute enable 0: soft mute disable (default) 1: soft mute enable ad1hpfn: adc1 hpf enable for dc offset cancelling 0: hpf enable (default) 1: hpf disable ad2hpfn: adc2 hpf enable for dc offset cancelling 0: hpf enable (default) 1: hpf disable admhpfn: adcm hpf enable for dc offset cancelling 0: hpf enable (default) 1: hpf disable
[ak 4601 ] 016000391 - e - 0 1 - 100 - 201 6 / 12 addr register name d7 d6 d5 d4 d3 d2 d1 d0 00 6 d dac1 lch digital volume volda1l[7:0] 00 6 e dac1 rch digital volume volda1r[7:0] 00 6 f dac2 lch digital volume volda2l[7:0] 0070 dac2 rch digital volume volda2r[7:0] 0071 dac 3 lch digital volume volda 3 l[7:0] 0072 dac 3 r ch digital volume volda 3 r[7:0] r/w r/w default 18h volda1l[7:0]: lch digital volume setting of dac1 ( table 53 ) default: 18h (0db) volda1r[7:0]: rch digital volume setting of dac1 ( table 53 ) default: 18h (0db) volda2l[7:0]: lch digital volume setting of dac2 ( table 53 ) default: 18h (0db) volda2r[7:0]: rch digital volume setting of dac2 ( table 53 ) default: 18h (0db) volda3l[7:0]: lch digital volume setting of dac3 ( table 53 ) default: 18h (0db) volda3r[7:0]: rch digital volume setting of dac3 ( table 53 ) default: 18h (0db) addr register name d7 d6 d5 d4 d3 d2 d1 d0 00 73 dac mute & filter setting atspda da1mute da2mute da3mute 0 dsmn dasd dasl r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 1 0 atspda: dac digital volume transition time setting ( table 54 ) 0: 4 /fs (default) 1: 16 /fs da1mute: dac1 soft mute enable 0: soft mute disable (default) 1: soft mute enable da2mute: dac2 soft mute enable 0: soft mute disable (default) 1: soft mute enable da3mute: dac3 soft mute enable 0: soft mute disable (default) 1: soft mute enable dsmn: sampling clock setting for delta sigma module of dac 0: 12.288mhz / 11.2896mhz fixed (default) 1: fs based dasd, da sl: dac digital filter select ( table 57 ) 00: sharp roll - off filter 01: slow roll - off filter 10: short delay sharp roll - off filter (default ) 11: short delay slow roll - off filter
[ak 4601 ] 016000391 - e - 0 1 - 101 - 201 6 / 12 addr register name d7 d6 d5 d4 d3 d2 d1 d0 00 74 dac dem setting 0 dem3[1:0] dem2[1:0] dem1[1:0] r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 1 0 1 0 1 dem1[1:0]: de - emphasis filter setting of dac1 ( table 58 ) 00: 44.1khz 01: off (default) 10: 48khz 11: 32khz dem2[1:0]: de - emphasis filter setting of dac2 ( table 58 ) 00: 44.1khz 01: off (default) 10: 48khz 11: 32khz dem3[1:0]: de - emphasis filter setting of dac3 ( table 58 ) 00: 44.1khz 01: off (default) 10: 48khz 11: 32khz
[ak 4601 ] 016000391 - e - 0 1 - 102 - 201 6 / 12 addr [hex] register name d7 d6 d5 d4 d3 d2 d1 d0 0075 vol 1 lch digital volume vol1l[ 7 :0] 0076 vol 1 r ch digital volume vol1 r [ 7: 0] 0077 vol2 lch digital volume vol 2 l[ 7 :0] 00 78 vol2 r ch digital volume vol 2r [ 7 :0] 00 79 vol3 lch digital volume vol 3 l[ 7 :0] 00 7a vol3 r ch digital volume vol 3r [ 7 :0] r/w r/w default 18h vol1l[7:0]: lch digital volume setting of vol1 ( table 36 ) defau lt: 18 h (0db) vol1r[7:0]: rch digital volume setting of vol1 ( table 36 ) default: 18 h (0db) vol2l[7:0]: lch digital volume setting of vol2 ( table 36 ) default : 18 h (0db) vol2r[7:0]: rch digital volume setting of vol2 ( table 36 ) default: 18 h (0db) vol3l[7:0]: lch digital volume setting of vol3 ( table 36 ) default: 18 h (0db) vol3r[7:0]: rch digital volume setting of vol3 ( table 36 ) default: 18 h (0db) addr register name d7 d6 d5 d4 d3 d2 d1 d0 00 7f vol setting atspvol 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 atspvol : digital volume transition speed setting of vol ( table 37 ) 0: 4 /fs (default) 1: 16 /fs addr register name d7 d6 d5 d4 d3 d2 d1 d0 00 83 sto flag setting 1 0 plllocke 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 plllocke: s to bit setting of pll lock signal 0: do not output to sto bit (default) 1: output to sto bit
[ak 4601 ] 016000391 - e - 0 1 - 103 - 201 6 / 12 addr register name d7 d6 d5 d4 d3 d2 d1 d0 00 8a power management 1 0 pmad1 pmad2 pmadm pmda1 pmda2 pmda 3 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 pmad1: adc1 power management setting 0: power s a ve mode (default) 1: normal operation pmad2: adc2 power management setting 0: power s a ve mode (default) 1: normal operation pmadm: adcm power management setting 0: power s a ve mode (default) 1: normal operation pmdax(x=1~3): dac1~3 power management setting 0: power s a ve mode (default) 1: normal operation addr register name d7 d6 d5 d4 d3 d2 d1 d0 00 8c reset control 0 0 1 cresetn 0 hresetn r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 1 0 0 0 0 0 cresetn: adc1 and codec reset 0: adc1 and codec reset (default) 1: reset release codec means adc2, adc, dac1, dac2 and dac3 . hresetn: hub reset 0: hub reset (default) all adc1/2, adcm, dac1 /2/3 and serial signal bus ar e reset 1: hub reset release read only registers addr [hex] register name d7 d6 d5 d4 d3 d2 d1 d0 0102 status read out 0 sto 0 default 0 1 0 0 0 0 0 0 sto: sto bit status read 0: error state 1: normal operation (default)
[ak 4601 ] 016000391 - e - 0 1 - 104 - 201 6 / 12 13. recommended external circuits connection diagram 1. i 2 c interface figure 73 . i 2 c interface connection example 7 digital io 1.8 3.3 v t vdd ak 4601 10 ? 0.1 ? dvss 1/dvss2 6 , 20 19 digital core 3.3 v l vdd 10 ? 0.1 ? avdrv 2.2 ? 46 aout1r 4 3 aout1l 4 4 aout2l aout2r 45 17 s da scl 15 14 up pdn reset control csn 13 h i2cfil 16 h or l 18 36 ainmp/ainm 37 ainmn 33 a in 5 l 34 gndin5 35 ain5 r 31 ain2lp/ain3l 32 ain2ln/ain4l 29 ain2rp/ain3r 30 ain2r n /ain4r 26 ain 1 l/inp1 25 inn1 28 ain 1 r/inp2 27 inn2 24 23 mpwr1 mpwr 2 mpref 22 1 ? 2k 2k 2k 2k 4 1 vrefh 3 8 analog +3.3 v avdd 10 ? 0.1 ? vcom 4 0 2.2 ? vrefl avss 4 2 3 9 10 ? 0.1 ? sdout1 5 sdin1 4 sdin2 9 sdout2 8 lrck1 3 bick1 2 lrck2 /sdout3 1 0 bick2 /sdin3 1 1 audio i/f clock & testi 21 l 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 u 1 u 1 u 1 u mcki 12 aout3l aout3r 47 48 clko 1
[ak 4601 ] 016000391 - e - 0 1 - 105 - 201 6 / 12 2 . spi interface figure 74 . spi interface connection example 7 digital io 1.8 3.3 v t vdd ak 4601 10 ? 0.1 ? dvss 1/dvss2 6 , 20 19 digital core 3.3 v l vdd 10 ? 0.1 ? avdrv 2.2 ? 46 aout1r 4 3 aout1l 4 4 aout2l aout2r 45 17 s o scl k 15 14 up pdn reset control csn 13 si 16 18 36 ainmp/ainm 37 ainmn 33 a in 5 l 34 gndin5 35 ain5 r 31 ain2lp/ain3l 32 ain2ln/ain4l 29 ain2rp/ain3r 30 ain2r n /ain4r 26 ain 1 l/inp1 25 inn1 28 ain 1 r/inp2 27 inn2 24 23 mpwr1 mpwr2 mpref 22 1 ? 2k 2k 2k 2k 4 1 vrefh 3 8 analog +3.3 v avdd 10 ? 0.1 ? vcom 4 0 2.2 ? vrefl avss 4 2 3 9 10 ? 0.1 ? sdout1 5 sdin1 4 sdin2 9 sdout2 8 lrck1 3 bick1 2 lrck2 /sdout3 1 0 bick2 /sdin3 1 1 audio i/f clock & testi 21 l 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1u 1u 1 u 1 u mcki 12 aout3l aout3r 47 48 clko 1
[ak 4601 ] 016000391 - e - 0 1 - 106 - 201 6 / 12 peripheral circuit 1. ground avss, dvss1 and dvss2 should be connected to the same ground. decoupling capacitors, pa rticularly capacitors of small capacity, should be placed at positions as close as possible to the AK4601 . 2. reference voltage the avdd voltage controls analog signal range. vcom is a common voltage of this chip and the vcom pin outputs avdd/2. a 2.2f capacitor should be conn ected between the vcom pin and a vss. do not connect the vcom pin to any external devices. digital signal lines, especially clock signal line should be kept away as far as possible from this pin in order to avoid unwanted coupling into the AK4601 . 3. analog input the analog input signal is input to the analog modulator of the AK4601 . when avdd = 3.3v and a vss = 0.0v, the input voltage range at d ifferential input pin is 2. 3 0vpp or 2. 83 vpp (typ.) and 2.30vpp or 2.83vpp (typ.) at single - ended input pin . t he output code format is 2's complements. the internal hpf removes the dc offset . after power - down is released, the internal operating point level avdd/2 occurs on analog input pins of the AK4601 . concerning the internal operating point formation circuit, each input pin has impedance of 2 5 k ? (typ). the pins that are connected to ac coupling capacitors require start - up time (time constant). the AK4601 samples the analog inputs at 6.144 mhz when fs=48 khz. digital fi l ters remove noise around from 30khz to 6.114mhz. the AK4601 includes an anti - aliasing filter (rc filter) . this filter attenuates noises around 6.114mhz ~ 6.144 mhz, which are not removed by the digital fil ters. therefore n o external low - pass filter is needed in front of the adc since most of audio signals do not have a large noise around 6.114 mhz . however, an external low - pass filter should be connected before the adc for the signal which has large out - of - band noise such as d/a converted sign als. the analog power supply to the AK4601 is +3.3v typical. voltage of avdd + 0.3v or larger , voltage of a vss - 0.3v or smaller , and current of 10ma or larger must not be applied to analog input pins. excessive current will damage the internal protection circuit and will cause latch - up, damaging the ic. accordingly, if the external analog circuit voltage is 15v, the analog input pins must be protected from signals which are equal or larger than absolute maximum rating s . figure 75 . input buffer circuit example at fs=48khz ( differential input ) inp* 10k 10k 10k 10k i nn* signal + - - + 2. 3 0 vp p / 2.83vpp 2. 3 0 vp p / 2.83vpp +10v 1 u 1 u + + - 10v 22 u + 68p 68p
[ak 4601 ] 016000391 - e - 0 1 - 107 - 201 6 / 12 4. analog output the analog output is single - ended and the output signal range is typically 0. 86 x avdd vpp centered on v com . the digital input data format is two s compliment. positive full - scale output corre sponds to 7ffff ff fh (@ 32 bit) inpu t code, negative full scale is 80 00 0000h (@ 32 bit) and vcom voltage ideally is 000 00 000h (@ 32 bit) . the out - of - band noise (shaping noise) generated by the internal delta - sigma modulator is attenuated by an integrated switched capacitor filter (scf) and a continuous time filter (ctf). 5. connection to digital circuit to minimize the noise from digital circuits, the digital output of the AK4601 must be connected to cmos or low voltage logic ics such as 74hc and 74ac for cmos and 74lv, 74lv - a, 74alvc and 74avc for low voltage logic ics.
[ak 4601 ] 016000391 - e - 0 1 - 108 - 201 6 / 12 14. package outline dimensions material and lead finish package: epoxy lead frame: copper terminal surface treatment : s oldering (pb free) plate 1 12 48 13 7.0 0.2 9.0 0.2 7.0 0.2 9.0 0.2 0.22 ?? 0. 08 48 - pin lqfp(unit: mm) 0.10 37 24 25 36 0.09 ? ? 0. 20 1.40 ?? 0.05 0.13 ?? 0. 13 1.70max 0 ?? 10 0.10 0.30 ~ 0. 75 0.5 s s m
[ak 4601 ] 016000391 - e - 0 1 - 109 - 201 6 / 12 ma rking 1) pin #1 indication 2) date code: xxxxxxx(7 digits) 3) mark ing code: AK4601 vq 4) asahi kasei logo 15. ordering guide ordering guide AK4601 - 40 ? +85 ? c 48 - p in l qf p (0.5mm pitch) akd460 1 evaluation board for the AK4601 ak 46 01 v q xxxxxxx 1
[ak 4601 ] 016000391 - e - 0 1 - 110 - 201 6 / 12 16. revision history date (y/m/d) revision reason page contents 1 6 / 03 / 23 00 first edition 1 6 / 12 / 0 8 0 1 error correct ion 5 figure of pdn pin i/o pin input pin 102 atspvol: digital volume transition speed setting of vol ( table 37 ) 0: 1 /fs (default) 4 /fs (default) 1: 4 /fs 16 /fs
[ak 4601 ] 016000391 - e - 0 1 - 111 - 201 6 / 12 important notice 0. asahi kasei microdevices corporation (akm) reserves the right to make changes to the information contained in this document without notice. when you consider any use or application of akm product stipulated in this document ( product ) , please make inquiries the sales office of akm or authorized d istributor s as to current status of the products. 1. all information included in this document are provided only to illustrate the operation and application examples of akm products . akm neither makes warranties or representations with respect to the accur acy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of akm or any third party with respect to the information in this document. you are fully responsible for use o f such information contained in this document in your product design or applications . akm assumes no liability for any losses incurred by you or third parties arising from the use of such information in your product design or applications. 2. the product is neither intended nor warranted for use in equipment or systems that require extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may cause loss of human life, bodily injury, serious property damage or seriou s public impact , including but not limited to, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to control combustions or explosions, safety devices, elevators and escalators, devices related to electric power, and equipment used in finance - related fields. do not use product for the above use unless specifically agreed by akm in writing . 3. tho ugh akm works continually to improve the products quality and reliability, you are responsible for complying with safety standards and for providing adequate designs and safeguards for your hardware, software and systems which minimize risk and avoid situ ations in which a malfunction or failure of the product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. 4. do not use or otherwise make available the product or related technology or any information c ontained in this document for any military purposes, including without limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass destruction weapons). when ex porting the p roducts or related technology or any information contained in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. the p roducts and related te chnology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 5. please contact akm sales representative for details as to environmental matters such as the rohs compatibility of the product. please use the product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the eu rohs directive. akm assu mes no liability for damages or losses occurring as a result of noncompliance with applicable laws and regulations. 6. resale of the product with provisions different from the statement and/or technical features set forth in this document shall immediately void any warranty granted by akm for the product and shall not create or extend in any manner whatsoever , any liability of akm. 7. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of akm .

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